[RFC net-next v5 1/3] net: ethernet: mtk_eth_soc: Add register definitions for RSS and LRO

Frank Wunderlich
2025-12-19T15:12:41Z

From: Mason Chang <mason-cw.chang@mediatek.com>

Add definitions for Receive Side Scaling and Large Receive Offload support.

Signed-off-by: Mason Chang <mason-cw.chang@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 23 +++++++++++++++
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 32 +++++++++++++++------
2 files changed, 46 insertions(+), 9 deletions(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index e68997a29191..243ff16fd15e 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -50,13 +50,18 @@ static const struct mtk_reg_map mtk_reg_map = {
.rx_ptr = 0x0900,
.rx_cnt_cfg = 0x0904,
.pcrx_ptr = 0x0908,
+ .lro_ctrl_dw0 = 0x0980,
.glo_cfg = 0x0a04,
.rst_idx = 0x0a08,
.delay_irq = 0x0a0c,
.irq_status = 0x0a20,
.irq_mask = 0x0a28,
.adma_rx_dbg0 = 0x0a38,
+ .lro_alt_score_delta = 0x0a4c,
.int_grp = 0x0a50,
+ .lro_rx1_dly_int = 0x0a70,
+ .lro_ring_dip_dw0 = 0x0b04,
+ .lro_ring_ctrl_dw1 = 0x0b28,
},
.qdma = {
.qtx_cfg = 0x1800,
@@ -113,6 +118,7 @@ static const struct mtk_reg_map mt7986_reg_map = {
.tx_irq_mask = 0x461c,
.tx_irq_status = 0x4618,
.pdma = {
+ .rss_glo_cfg = 0x2800,
.rx_ptr = 0x4100,
.rx_cnt_cfg = 0x4104,
.pcrx_ptr = 0x4108,
@@ -123,6 +129,12 @@ static const struct mtk_reg_map mt7986_reg_map = {
.irq_mask = 0x4228,
.adma_rx_dbg0 = 0x4238,
.int_grp = 0x4250,
+ .int_grp3 = 0x422c,
+ .lro_ctrl_dw0 = 0x4180,
+ .lro_alt_score_delta = 0x424c,
+ .lro_rx1_dly_int = 0x4270,
+ .lro_ring_dip_dw0 = 0x4304,
+ .lro_ring_ctrl_dw1 = 0x4328,
},
.qdma = {
.qtx_cfg = 0x4400,
@@ -170,10 +182,21 @@ static const struct mtk_reg_map mt7988_reg_map = {
.glo_cfg = 0x6a04,
.rst_idx = 0x6a08,
.delay_irq = 0x6a0c,
+ .rx_cfg = 0x6a10,
.irq_status = 0x6a20,
.irq_mask = 0x6a28,
.adma_rx_dbg0 = 0x6a38,
.int_grp = 0x6a50,
+ .int_grp3 = 0x6a58,
+ .tx_delay_irq = 0x6ab0,
+ .rx_delay_irq = 0x6ac0,
+ .lro_ctrl_dw0 = 0x6c08,
+ .lro_alt_score_delta = 0x6c1c,
+ .lro_ring_dip_dw0 = 0x6c14,
+ .lro_ring_ctrl_dw1 = 0x6c38,
+ .lro_alt_dbg = 0x6c40,
+ .lro_alt_dbg_data = 0x6c44,
+ .rss_glo_cfg = 0x7000,
},
.qdma = {
.qtx_cfg = 0x4400,
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 0168e2fbc619..334625814b97 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -1143,16 +1143,30 @@ struct mtk_reg_map {
u32 tx_irq_mask;
u32 tx_irq_status;
struct {
- u32 rx_ptr; /* rx base pointer */
- u32 rx_cnt_cfg; /* rx max count configuration */
- u32 pcrx_ptr; /* rx cpu pointer */
- u32 glo_cfg; /* global configuration */
- u32 rst_idx; /* reset index */
- u32 delay_irq; /* delay interrupt */
- u32 irq_status; /* interrupt status */
- u32 irq_mask; /* interrupt mask */
+ u32 rx_ptr; /* rx base pointer */
+ u32 rx_cnt_cfg; /* rx max count configuration */
+ u32 pcrx_ptr; /* rx cpu pointer */
+ u32 pdrx_ptr; /* rx dma pointer */
+ u32 glo_cfg; /* global configuration */
+ u32 rst_idx; /* reset index */
+ u32 rx_cfg; /* rx dma configuration */
+ u32 delay_irq; /* delay interrupt */
+ u32 irq_status; /* interrupt status */
+ u32 irq_mask; /* interrupt mask */
u32 adma_rx_dbg0;
- u32 int_grp;
+ u32 int_grp; /* interrupt group1 */
+ u32 int_grp3; /* interrupt group3 */
+ u32 tx_delay_irq; /* tx delay interrupt */
+ u32 rx_delay_irq; /* rx delay interrupt */
+ u32 lro_ctrl_dw0; /* lro ctrl dword0 */
+ u32 lro_alt_score_delta; /* lro auto-learn score delta */
+ u32 lro_rx1_dly_int; /* lro rx ring1 delay interrupt */
+ u32 lro_ring_dip_dw0; /* lro ring dip dword0 */
+ u32 lro_ring_ctrl_dw1; /* lro ring ctrl dword1 */
+ u32 lro_alt_dbg; /* lro auto-learn debug */
+ u32 lro_alt_dbg_data; /* lro auto-learn debug data */
+ u32 rss_glo_cfg; /* rss global configuration */
+
} pdma;
struct {
u32 qtx_cfg; /* tx queue configuration */
--
2.43.0