[PATCH 00/12] Add RTC support for the Renesas RZ/G3S SoC

[PATCH 00/12] Add RTC support for the Renesas RZ/G3S SoC

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Hi,

On the Renesas RZ/G3S SoC the RTC clock is provided by the VBATTB
IP. A 32 KHz crystall oscillator could be connected to the VBATTB
input pins. The logic to control this clock (and pass it to RTC)
is inside the VBATTB IP. For this, the clk-vbattb driver was added
(patches 01-04/12).

Patches 05-06/12 add the RTC driver.

Patches 07-10/12 update the device trees with proper nodes to enable RTC.

Patches 11-12/12 enable proper config flags for RTC to work on RZ/G3S SoC.

Thank you,
Claudiu Beznea

Claudiu Beznea (12):
  clk: renesas: r9a08g045: Add clock, reset and power domain support for
    the VBATTB IP
  dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB
    clock driver
  dt-bindings: mfd: renesas,rzg3s-vbattb: Document VBATTB
  clk: renesas: clk-vbattb: Add VBATTB clock driver
  dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC
  rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S
    SoC
  arm64: dts: renesas: r9a08g045: Add VBATTB node
  arm64: dts: renesas: r9a08g045: Add RTC node
  arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB clock
  arm64: dts: renesas: rzg3s-smarc-som: Enable RTC
  arm64: defconfig: Enable VBATTB clock flag
  arm64: defconfig: Enable Renesas RTCA-3 flag

 .../clock/renesas,rzg3s-vbattb-clk.yaml       |  90 ++
 .../bindings/mfd/renesas,rzg3s-vbattb.yaml    |  99 ++
 .../bindings/rtc/renesas,rzg3s-rtc.yaml       |  60 ++
 MAINTAINERS                                   |   8 +
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |  44 +
 .../boot/dts/renesas/rzg3s-smarc-som.dtsi     |  17 +
 arch/arm64/configs/defconfig                  |   2 +
 drivers/clk/renesas/Kconfig                   |   4 +
 drivers/clk/renesas/Makefile                  |   1 +
 drivers/clk/renesas/clk-vbattb.c              | 202 ++++
 drivers/clk/renesas/r9a08g045-cpg.c           |   6 +
 drivers/rtc/Kconfig                           |  10 +
 drivers/rtc/Makefile                          |   1 +
 drivers/rtc/rtc-renesas-rtca3.c               | 891 ++++++++++++++++++
 14 files changed, 1435 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
 create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzg3s-vbattb.yaml
 create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
 create mode 100644 drivers/clk/renesas/clk-vbattb.c
 create mode 100644 drivers/rtc/rtc-renesas-rtca3.c

-- 
2.39.2

[PATCH 01/12] clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB)
that generates the RTC clock. Add clock, reset and power domain support
for it.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/r9a08g045-cpg.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index b068733b145f..2ae97c29c377 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -215,6 +215,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
 	DEF_MOD("eth1_refclk",		R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
 	DEF_MOD("scif0_clk_pck",	R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
 	DEF_MOD("gpio_hclk",		R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
+	DEF_MOD("vbat_bclk",		R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
 };
 
 static const struct rzg2l_reset r9a08g045_resets[] = {
@@ -231,6 +232,7 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
 	DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
 	DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
 	DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
+	DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
 };
 
 static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
@@ -238,6 +240,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
 	MOD_CLK_BASE + R9A08G045_IA55_PCLK,
 	MOD_CLK_BASE + R9A08G045_IA55_CLK,
 	MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
+	MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
 };
 
 static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
@@ -275,6 +278,9 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
 	DEF_PD("scif0",		R9A08G045_PD_SCIF0,
 				DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
 				RZG2L_PD_F_NONE),
+	DEF_PD("vbat",		R9A08G045_PD_VBAT,
+				DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
+				RZG2L_PD_F_ALWAYS_ON),
 };
 
 const struct rzg2l_cpg_info r9a08g045_cpg_info = {
-- 
2.39.2

[PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feeds
the RTC and the tamper detector. Add documentation for the VBATTB clock
driver.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 .../clock/renesas,rzg3s-vbattb-clk.yaml       | 90 +++++++++++++++++++
 1 file changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
new file mode 100644
index 000000000000..ef52a0c0f874
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,rzg3s-vbattb-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas VBATTB clock
+
+maintainers:
+  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+
+description:
+  Renesas VBATTB module is an always on powered module (backed by battery) which
+  generates a clock (VBATTCLK). This clocks feeds the RTC and the tamper detector
+  modules.
+
+properties:
+  compatible:
+    const: renesas,rzg3s-vbattb-clk
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: VBATTB module clock
+      - description: VBATTB input xtal
+
+  clock-names:
+    items:
+      - const: bclk
+      - const: vbattb_xtal
+
+  '#clock-cells':
+    const: 0
+
+  power-domains:
+    maxItems: 1
+
+  renesas,vbattb-load-nanofarads:
+    description: load capacitance of the on board xtal
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [ 4000, 7000, 9000, 12500 ]
+
+  renesas,vbattb-osc-bypass:
+    description: set when external clock is connected to RTXOUT pin
+    type: boolean
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+  - '#clock-cells'
+  - renesas,vbattb-load-nanofarads
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a08g045-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    vbattb: vbattb@1005c000 {
+        compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
+        reg = <0x1005c000 0x1000>;
+        ranges = <0 0 0x1005c000 0 0x1000>;
+        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "tampdi";
+        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
+        clock-names = "bclk";
+        power-domains = <&cpg>;
+        resets = <&cpg R9A08G045_VBAT_BRESETN>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        status = "disabled";
+
+        vbattclk: clock-controller@1c {
+            compatible = "renesas,rzg3s-vbattb-clk";
+            reg = <0 0x1c 0 0x10>;
+            clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
+            clock-names = "bclk", "vbattb_xtal";
+            #clock-cells = <0>;
+            power-domains = <&cpg>;
+            status = "disabled";
+        };
+    };
+
+...
-- 
2.39.2

[PATCH 03/12] dt-bindings: mfd: renesas,rzg3s-vbattb: Document VBATTB

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC,
the tamper detector and a small general usage memory of 128B. Add
documentation for it.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 .../bindings/mfd/renesas,rzg3s-vbattb.yaml    | 99 +++++++++++++++++++
 1 file changed, 99 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzg3s-vbattb.yaml

diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg3s-vbattb.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg3s-vbattb.yaml
new file mode 100644
index 000000000000..c0259e557dc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/renesas,rzg3s-vbattb.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/renesas,rzg3s-vbattb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Battery Backup Function (VBATTB)
+
+description:
+  Renesas VBATTB is a module which controls the RTC clock (VBATTCLK), tamper
+  detection logic and a small general usage memory (128B).
+
+maintainers:
+  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+
+properties:
+  compatible:
+    items:
+      - const: renesas,rzg3s-vbattb
+      - const: syscon
+      - const: simple-mfd
+
+  reg:
+    maxItems: 1
+
+  ranges: true
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 2
+
+patternProperties:
+  "^clock-controller@[0-9a-f]+$":
+    $ref: /schemas/clock/renesas,rzg3s-vbattb-clk.yaml#
+    description: VBATTCLK clock
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - power-domains
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a08g045-cpg.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    vbattb: vbattb@1005c000 {
+        compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
+        reg = <0x1005c000 0x1000>;
+        ranges = <0 0 0x1005c000 0 0x1000>;
+        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "tampdi";
+        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
+        clock-names = "bclk";
+        power-domains = <&cpg>;
+        resets = <&cpg R9A08G045_VBAT_BRESETN>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+        status = "disabled";
+
+        vbattclk: clock-controller@1c {
+            compatible = "renesas,rzg3s-vbattb-clk";
+            reg = <0 0x1c 0 0x10>;
+            clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
+            clock-names = "bclk", "vbattb_xtal";
+            #clock-cells = <0>;
+            power-domains = <&cpg>;
+            status = "disabled";
+        };
+    };
+
+...
-- 
2.39.2

[PATCH 04/12] clk: renesas: clk-vbattb: Add VBATTB clock driver

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used
by the RTC. The input to the VBATTB could be a 32KHz crystal connected
to both the RTXIN and RTXOUT pins or an external clock connected to
RTXOUT pin. In case an external clock is connected to the RTXOUT pin the
renesas,vbattb-osc-bypass DT property need to be used when describing the
node.

The load capacitance of the on-board oscillator need to be configured with
renesas,vbattb-load-nanofarads DT property.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 drivers/clk/renesas/Kconfig      |   4 +
 drivers/clk/renesas/Makefile     |   1 +
 drivers/clk/renesas/clk-vbattb.c | 202 +++++++++++++++++++++++++++++++
 3 files changed, 207 insertions(+)
 create mode 100644 drivers/clk/renesas/clk-vbattb.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index d252150402e8..1dc38e3a8326 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -228,6 +228,10 @@ config CLK_RZG2L
 	bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
 	select RESET_CONTROLLER
 
+config CLK_VBATTB
+	bool "Renesas VBATTB clock controller"
+	select RESET_CONTROLLER
+
 # Generic
 config CLK_RENESAS_CPG_MSSR
 	bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index f7e18679c3b8..e9e487f53577 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_CLK_RZG2L)			+= rzg2l-cpg.o
 obj-$(CONFIG_CLK_RENESAS_CPG_MSSR)	+= renesas-cpg-mssr.o
 obj-$(CONFIG_CLK_RENESAS_CPG_MSTP)	+= clk-mstp.o
 obj-$(CONFIG_CLK_RENESAS_DIV6)		+= clk-div6.o
+obj-$(CONFIG_CLK_VBATTB)		+= clk-vbattb.o
diff --git a/drivers/clk/renesas/clk-vbattb.c b/drivers/clk/renesas/clk-vbattb.c
new file mode 100644
index 000000000000..0a5cc886e89c
--- /dev/null
+++ b/drivers/clk/renesas/clk-vbattb.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * VBATTB clock driver
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#define VBATTB_BKSCCR			0x1c
+#define VBATTB_BKSCCR_SOSEL		BIT(6)
+#define VBATTB_SOSCCR2			0x24
+#define VBATTB_SOSCCR2_SOSTP2		BIT(0)
+#define VBATTB_XOSCCR			0x30
+#define VBATTB_XOSCCR_OUTEN		BIT(16)
+#define VBATTB_XOSCCR_XSEL		GENMASK(1, 0)
+#define VBATTB_XOSCCR_XSEL_4_PF		0x0
+#define VBATTB_XOSCCR_XSEL_7_PF		0x1
+#define VBATTB_XOSCCR_XSEL_9_PF		0x2
+#define VBATTB_XOSCCR_XSEL_12_5_PF	0x3
+
+/**
+ * struct vbattb_clk - VBATTB clock data structure
+ * @regmap: regmap
+ * @hw: clk hw
+ * @lock: device lock
+ * @load_capacitance: load capacitance
+ */
+struct vbattb_clk {
+	struct regmap *regmap;
+	struct clk_hw hw;
+	spinlock_t lock;
+	u8 load_capacitance;
+};
+
+#define to_vbattb_clk(_hw) container_of(_hw, struct vbattb_clk, hw)
+
+static int vbattb_clk_enable(struct clk_hw *hw)
+{
+	struct vbattb_clk *vbclk = to_vbattb_clk(hw);
+	struct regmap *regmap = vbclk->regmap;
+
+	spin_lock(&vbclk->lock);
+	regmap_update_bits(regmap, VBATTB_SOSCCR2, VBATTB_SOSCCR2_SOSTP2, 0);
+	regmap_update_bits(regmap, VBATTB_XOSCCR, VBATTB_XOSCCR_OUTEN | VBATTB_XOSCCR_XSEL,
+			   VBATTB_XOSCCR_OUTEN | vbclk->load_capacitance);
+	spin_unlock(&vbclk->lock);
+
+	return 0;
+}
+
+static void vbattb_clk_disable(struct clk_hw *hw)
+{
+	struct vbattb_clk *vbclk = to_vbattb_clk(hw);
+	struct regmap *regmap = vbclk->regmap;
+
+	spin_lock(&vbclk->lock);
+	regmap_update_bits(regmap, VBATTB_XOSCCR, VBATTB_XOSCCR_OUTEN, 0);
+	regmap_update_bits(regmap, VBATTB_SOSCCR2, VBATTB_SOSCCR2_SOSTP2, VBATTB_SOSCCR2_SOSTP2);
+	spin_unlock(&vbclk->lock);
+}
+
+static int vbattb_clk_is_enabled(struct clk_hw *hw)
+{
+	struct vbattb_clk *vbclk = to_vbattb_clk(hw);
+	struct regmap *regmap = vbclk->regmap;
+	unsigned int xosccr, sosccr2;
+	int ret;
+
+	spin_lock(&vbclk->lock);
+	ret = regmap_read(regmap, VBATTB_XOSCCR, &xosccr);
+	if (ret)
+		goto unlock;
+
+	ret = regmap_read(regmap, VBATTB_SOSCCR2, &sosccr2);
+unlock:
+	spin_unlock(&vbclk->lock);
+
+	if (ret)
+		return 0;
+
+	return ((xosccr & VBATTB_XOSCCR_OUTEN) && !(sosccr2 & VBATTB_SOSCCR2_SOSTP2));
+}
+
+static const struct clk_ops vbattb_clk_ops = {
+	.enable = vbattb_clk_enable,
+	.disable = vbattb_clk_disable,
+	.is_enabled = vbattb_clk_is_enabled,
+};
+
+static int vbattb_clk_validate_load_capacitance(struct vbattb_clk *vbclk, u32 load_capacitance)
+{
+	switch (load_capacitance) {
+	case 4000:
+		vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_4_PF;
+		break;
+	case 7000:
+		vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_7_PF;
+		break;
+	case 9000:
+		vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_9_PF;
+		break;
+	case 12500:
+		vbclk->load_capacitance = VBATTB_XOSCCR_XSEL_12_5_PF;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int vbattb_clk_probe(struct platform_device *pdev)
+{
+	struct clk_parent_data parent_data = { .fw_name = "vbattb_xtal" };
+	struct device_node *np = pdev->dev.of_node;
+	struct device *dev = &pdev->dev;
+	struct clk_init_data init = {};
+	struct vbattb_clk *vbclk;
+	u32 load_capacitance;
+	struct clk_hw *hw;
+	bool bypass;
+	int ret;
+
+	vbclk = devm_kzalloc(dev, GFP_KERNEL, sizeof(*vbclk));
+	if (!vbclk)
+		return -ENOMEM;
+
+	vbclk->regmap = syscon_node_to_regmap(np->parent);
+	if (IS_ERR(vbclk->regmap))
+		return PTR_ERR(vbclk->regmap);
+
+	bypass = of_property_read_bool(np, "renesas,vbattb-osc-bypass");
+	ret = of_property_read_u32(np, "renesas,vbattb-load-nanofarads", &load_capacitance);
+	if (ret)
+		return ret;
+
+	ret = vbattb_clk_validate_load_capacitance(vbclk, load_capacitance);
+	if (ret)
+		return ret;
+
+	ret = devm_pm_runtime_enable(dev);
+	if (ret)
+		return ret;
+
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret)
+		return ret;
+
+	regmap_update_bits(vbclk->regmap, VBATTB_BKSCCR, VBATTB_BKSCCR_SOSEL,
+			   bypass ? VBATTB_BKSCCR_SOSEL : 0);
+
+	init.name = "vbattclk";
+	init.ops = &vbattb_clk_ops;
+	init.parent_data = &parent_data;
+	init.num_parents = 1;
+	init.flags = 0;
+
+	vbclk->hw.init = &init;
+	hw = &vbclk->hw;
+
+	spin_lock_init(&vbclk->lock);
+
+	ret = devm_clk_hw_register(dev, hw);
+	if (ret)
+		goto rpm_put;
+
+	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
+	if (ret)
+		goto rpm_put;
+
+	return 0;
+
+rpm_put:
+	pm_runtime_put(dev);
+	return ret;
+}
+
+static const struct of_device_id vbattb_clk_match[] = {
+	{ .compatible = "renesas,rzg3s-vbattb-clk" },
+	{ /* sentinel */ }
+};
+
+static struct platform_driver vbattb_clk_driver = {
+	.driver		= {
+		.name	= "vbattb-clk",
+		.of_match_table = vbattb_clk_match,
+	},
+	.probe = vbattb_clk_probe,
+};
+module_platform_driver(vbattb_clk_driver);
+
+MODULE_DESCRIPTION("Renesas VBATTB Clock Driver");
+MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>");
+MODULE_LICENSE("GPL");
-- 
2.39.2

[PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 .../bindings/rtc/renesas,rzg3s-rtc.yaml       | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml

diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
new file mode 100644
index 000000000000..0e17f8a36155
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/renesas,rzg3s-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Real Time Clock for Renesas RZ/G3S SoC
+
+maintainers:
+  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+
+properties:
+  compatible:
+    const: renesas,rzg3s-rtc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 3
+
+  interrupt-names:
+    items:
+      - const: alarm
+      - const: period
+      - const: carry
+
+  clocks:
+    maxItems: 1
+    description: RTC counter clock
+
+  clock-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    rtc: rtc@1004ec00 {
+        compatible = "renesas,rzg3s-rtc";
+        reg = <0x1004ec00 0x400>;
+        interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+        interrupt-names = "alarm", "period", "carry";
+        clocks = <&vbattclk>;
+        clock-names = "counter";
+        status = "disabled";
+    };
-- 
2.39.2

[PATCH 06/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count
mode and binary count mode (selectable though RCR2.CNTMD) capabilities,
alarm capabilities, clock error correction capabilities. It can generate
alarm, period, carry interrupts.

Add a driver for RTCA-3 IP. The driver implements calendar count mode (as
the conversion b/w RTC and system time is simpler, done with bcd2bin(),
bin2bcd()), read and set time, read and set alarm, read and set
an offset.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 MAINTAINERS                     |   8 +
 drivers/rtc/Kconfig             |  10 +
 drivers/rtc/Makefile            |   1 +
 drivers/rtc/rtc-renesas-rtca3.c | 891 ++++++++++++++++++++++++++++++++
 4 files changed, 910 insertions(+)
 create mode 100644 drivers/rtc/rtc-renesas-rtca3.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 670b8201973b..0b4bf350c416 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19173,6 +19173,14 @@ S:	Supported
 F:	Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
 F:	drivers/counter/rz-mtu3-cnt.c
 
+RENESAS RZ/G3S RTC DRIVER
+M:	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
+L:	linux-rtc@vger.kernel.org
+L:	linux-renesas-soc@vger.kernel.org
+S:	Supported
+F:	Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
+F:	drivers/rtc/rtc-renesas-rtca3.c
+
 RENESAS RZ/N1 A5PSW SWITCH DRIVER
 M:	Clément Léger <clement.leger@bootlin.com>
 L:	linux-renesas-soc@vger.kernel.org
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 2a95b05982ad..3b29b35e48e0 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1978,6 +1978,16 @@ config RTC_DRV_MA35D1
 	   This driver can also be built as a module, if so, the module
 	   will be called "rtc-ma35d1".
 
+config RTC_DRV_RENESAS_RTCA3
+	tristate "Renesas RTCA-3 RTC"
+	depends on ARCH_RENESAS
+	help
+	  If you say yes here you get support for the Renesas RTCA-3 RTC
+	  available on the Renesas RZ/G3S SoC.
+
+	  This driver can also be built as a module, if so, the module
+	  will be called "rtc-rtca3".
+
 comment "HID Sensor RTC drivers"
 
 config RTC_DRV_HID_SENSOR_TIME
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 3004e372f25f..52844f13b247 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -157,6 +157,7 @@ obj-$(CONFIG_RTC_DRV_RX8025)	+= rtc-rx8025.o
 obj-$(CONFIG_RTC_DRV_RX8111)	+= rtc-rx8111.o
 obj-$(CONFIG_RTC_DRV_RX8581)	+= rtc-rx8581.o
 obj-$(CONFIG_RTC_DRV_RZN1)	+= rtc-rzn1.o
+obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3)	+= rtc-renesas-rtca3.o
 obj-$(CONFIG_RTC_DRV_S35390A)	+= rtc-s35390a.o
 obj-$(CONFIG_RTC_DRV_S3C)	+= rtc-s3c.o
 obj-$(CONFIG_RTC_DRV_S5M)	+= rtc-s5m.o
diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c
new file mode 100644
index 000000000000..e2edf12d0c54
--- /dev/null
+++ b/drivers/rtc/rtc-renesas-rtca3.c
@@ -0,0 +1,891 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * On-Chip RTC Support available on RZ/G3S SoC
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#include <linux/bcd.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+
+/* Counter registers. */
+#define RTCA3_RSECCNT			0x2
+#define RTCA3_RSECCNT_SEC		GENMASK(6, 0)
+#define RTCA3_RMINCNT			0x4
+#define RTCA3_RMINCNT_MIN		GENMASK(6, 0)
+#define RTCA3_RHRCNT			0x6
+#define RTCA3_RHRCNT_HR			GENMASK(5, 0)
+#define RTCA3_RHRCNT_PM			BIT(6)
+#define RTCA3_RWKCNT			0x8
+#define RTCA3_RWKCNT_WK			GENMASK(2, 0)
+#define RTCA3_RDAYCNT			0xa
+#define RTCA3_RDAYCNT_DAY		GENMASK(5, 0)
+#define RTCA3_RMONCNT			0xc
+#define RTCA3_RMONCNT_MONTH		GENMASK(4, 0)
+#define RTCA3_RYRCNT			0xe
+#define RTCA3_RYRCNT_YEAR		GENMASK(7, 0)
+
+/* Alarm registers. */
+#define RTCA3_RSECAR			0x10
+#define RTCA3_RSECAR_SEC		GENMASK(6, 0)
+#define RTCA3_RMINAR			0x12
+#define RTCA3_RMINAR_MIN		GENMASK(6, 0)
+#define RTCA3_RHRAR			0x14
+#define RTCA3_RHRAR_HR			GENMASK(5, 0)
+#define RTCA3_RHRAR_PM			BIT(6)
+#define RTCA3_RWKAR			0x16
+#define RTCA3_RWKAR_DAYW		GENMASK(2, 0)
+#define RTCA3_RDAYAR			0x18
+#define RTCA3_RDAYAR_DATE		GENMASK(5, 0)
+#define RTCA3_RMONAR			0x1a
+#define RTCA3_RMONAR_MON		GENMASK(4, 0)
+#define RTCA3_RYRAR			0x1c
+#define RTCA3_RYRAR_YR			GENMASK(7, 0)
+#define RTCA3_RYRAREN			0x1e
+
+/* Alarm enable bit (for all alarm registers). */
+#define RTCA3_AR_ENB			BIT(7)
+
+/* Control registers. */
+#define RTCA3_RCR1			0x22
+#define RTCA3_RCR1_AIE			BIT(0)
+#define RTCA3_RCR1_CIE			BIT(1)
+#define RTCA3_RCR1_PIE			BIT(2)
+#define RTCA3_RCR1_PES			GENMASK(7, 4)
+#define RTCA3_RCR1_PES_1_64_SEC		0x8
+#define RTCA3_RCR2			0x24
+#define RTCA3_RCR2_START		BIT(0)
+#define RTCA3_RCR2_RESET		BIT(1)
+#define RTCA3_RCR2_AADJE		BIT(4)
+#define RTCA3_RCR2_ADJP			BIT(5)
+#define RTCA3_RCR2_HR24			BIT(6)
+#define RTCA3_RCR2_CNTMD		BIT(7)
+#define RTCA3_RSR			0x20
+#define RTCA3_RSR_AF			BIT(0)
+#define RTCA3_RSR_CF			BIT(1)
+#define RTCA3_RSR_PF			BIT(2)
+#define RTCA3_RADJ			0x2e
+#define RTCA3_RADJ_ADJ			GENMASK(5, 0)
+#define RTCA3_RADJ_ADJ_MAX		0x3f
+#define RTCA3_RADJ_PMADJ		GENMASK(7, 6)
+#define RTCA3_RADJ_PMADJ_NONE		0
+#define RTCA3_RADJ_PMADJ_ADD		1
+#define RTCA3_RADJ_PMADJ_SUB		2
+
+/* Polling operation timeouts. */
+#define RTCA3_DEFAULT_TIMEOUT_US	150
+#define RTCA3_IRQSET_TIMEOUT_US		5000
+#define RTCA3_START_TIMEOUT_US		150000
+#define RTCA3_RESET_TIMEOUT_US		200000
+
+/**
+ * enum rtca3_alrm_set_step - RTCA3 alarm set steps
+ * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step
+ * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step
+ * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step
+ */
+enum rtca3_alrm_set_step {
+	RTCA3_ALRM_SSTEP_DONE = 0,
+	RTCA3_ALRM_SSTEP_IRQ = 1,
+	RTCA3_ALRM_SSTEP_INIT = 3,
+};
+
+/**
+ * struct rtca3_ppb_per_cycle - PPB per cycle
+ * @ten_sec: PPB per cycle in 10 seconds adjutment mode
+ * @sixty_sec: PPB per cycle in 60 seconds adjustment mode
+ */
+struct rtca3_ppb_per_cycle {
+	int ten_sec;
+	int sixty_sec;
+};
+
+/**
+ * struct rtca3_priv - RTCA3 private data structure
+ * @base: base address
+ * @clk: RTC clock
+ * @rtc_dev: RTC device
+ * @set_alarm_completion: alarm setup completion
+ * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step)
+ * @lock: device lock
+ * @ppb: ppb per cycle for each the available adjustment modes
+ * @wakeup_irq: wakeup IRQ
+ */
+struct rtca3_priv {
+	void __iomem *base;
+	struct clk *clk;
+	struct rtc_device *rtc_dev;
+	struct completion set_alarm_completion;
+	atomic_t alrm_sstep;
+	spinlock_t lock;
+	struct rtca3_ppb_per_cycle ppb;
+	int wakeup_irq;
+};
+
+static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8 mask, u8 val)
+{
+	u8 tmp;
+
+	tmp = readb(priv->base + off);
+	tmp &= ~(mask);
+	tmp |= (val & mask);
+	writeb(tmp, priv->base + off);
+}
+
+static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv)
+{
+	u8 val, pending;
+
+	val = readb(priv->base + RTCA3_RSR);
+	pending = val & RTCA3_RSR_AF;
+	writeb(val & ~pending, priv->base + RTCA3_RSR);
+
+	if (pending)
+		rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF);
+
+	return pending;
+}
+
+static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id)
+{
+	struct rtca3_priv *priv = dev_id;
+	u8 pending;
+
+	spin_lock(&priv->lock);
+	pending = rtca3_alarm_handler_helper(priv);
+	spin_unlock(&priv->lock);
+
+	return IRQ_RETVAL(pending);
+}
+
+static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id)
+{
+	struct rtca3_priv *priv = dev_id;
+	u8 val, pending;
+
+	spin_lock(&priv->lock);
+
+	val = readb(priv->base + RTCA3_RSR);
+	pending = val & RTCA3_RSR_PF;
+
+	if (pending) {
+		writeb(val & ~pending, priv->base + RTCA3_RSR);
+
+		if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) {
+			/* Alarm setup in progress. */
+			atomic_dec(&priv->alrm_sstep);
+
+			if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) {
+				/*
+				 * We got 2 * 1/64 periodic interrupts. Disable
+				 * interrupt and let alarm setup continue.
+				 */
+				rtca3_byte_update_bits(priv, RTCA3_RCR1,
+						       RTCA3_RCR1_PIE, 0);
+				readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val,
+							  !(val & RTCA3_RCR1_PIE),
+							  10, RTCA3_DEFAULT_TIMEOUT_US);
+				complete(&priv->set_alarm_completion);
+			}
+		}
+	}
+
+	spin_unlock(&priv->lock);
+
+	return IRQ_RETVAL(pending);
+}
+
+static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv *priv, bool cnt)
+{
+	/* Offset b/w time and alarm registers. */
+	u8 offset = cnt ? 0 : 0xe;
+
+	/*
+	 * According to HW manual (section 22.6.4. Notes on writing to and
+	 * reading from registers) after writing to count registers, alarm
+	 * registers, year alarm enable register, bits RCR2.AADJE, AADJP,
+	 * and HR24 register, we need to do 3 empty reads before being
+	 * able to fetch the registers content.
+	 */
+	for (u8 i = 0; i < 3; i++) {
+		readb(priv->base + RTCA3_RSECCNT + offset);
+		readb(priv->base + RTCA3_RMINCNT + offset);
+		readb(priv->base + RTCA3_RHRCNT  + offset);
+		readb(priv->base + RTCA3_RWKCNT  + offset);
+		readb(priv->base + RTCA3_RDAYCNT + offset);
+		readw(priv->base + RTCA3_RYRCNT  + offset);
+		if (!cnt)
+			readb(priv->base + RTCA3_RYRAREN);
+	}
+}
+
+static int rtca3_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtca3_priv *priv = dev_get_drvdata(dev);
+	u8 sec, min, hour, wday, mday, month, tmp;
+	unsigned long flags;
+	u8 trials = 0;
+	int ret = 0;
+	u32 year100;
+	u16 year;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	tmp = readb(priv->base + RTCA3_RCR2);
+	if (!(tmp & RTCA3_RCR2_START)) {
+		ret = -EINVAL;
+		goto unlock;
+	}
+
+	do {
+		/* Clear carry interrupt. */
+		rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0);
+
+		/* Read counters. */
+		sec = readb(priv->base + RTCA3_RSECCNT);
+		min = readb(priv->base + RTCA3_RMINCNT);
+		hour = readb(priv->base + RTCA3_RHRCNT);
+		wday = readb(priv->base + RTCA3_RWKCNT);
+		mday = readb(priv->base + RTCA3_RDAYCNT);
+		month = readb(priv->base + RTCA3_RMONCNT);
+		year = readw(priv->base + RTCA3_RYRCNT);
+
+		tmp = readb(priv->base + RTCA3_RSR);
+
+		/*
+		 * We cannot generate carries due to reading 64Hz counter as
+		 * the driver doesn't implement carry, thus, carries will be
+		 * generated once per seconds. Add a timeout of 5 trials here
+		 * to avoid infinite loop, if any.
+		 */
+	} while ((tmp & RTCA3_RSR_CF) && ++trials < 5);
+
+	if (trials >= 5) {
+		ret = -ETIMEDOUT;
+		goto unlock;
+	}
+
+	tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec));
+	tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min));
+	tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour));
+	if (hour & RTCA3_RHRCNT_PM)
+		tm->tm_hour += 12;
+	tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday));
+	tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday));
+	tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1;
+	year = FIELD_GET(RTCA3_RYRCNT_YEAR, year);
+	year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20);
+	tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900;
+
+unlock:
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return ret;
+}
+
+static int rtca3_set_time(struct device *dev, struct rtc_time *tm)
+{
+	struct rtca3_priv *priv = dev_get_drvdata(dev);
+	unsigned long flags;
+	u8 rcr2, tmp;
+	int ret;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	/* Stop the RTC. */
+	rcr2 = readb(priv->base + RTCA3_RCR2);
+	writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2);
+	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
+					!(tmp & RTCA3_RCR2_START),
+					10, RTCA3_DEFAULT_TIMEOUT_US);
+	if (ret)
+		goto unlock;
+
+	/* Update time. */
+	writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT);
+	writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT);
+	if (tm->tm_hour > 12)
+		writeb(RTCA3_RHRCNT_PM | bin2bcd(tm->tm_hour - 12), priv->base + RTCA3_RHRCNT);
+	else
+		writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT);
+	writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT);
+	writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT);
+	writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT);
+	writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT);
+
+	/* Make sure we can read back the counters. */
+	rtca3_prepare_cntalrm_regs_for_read(priv, true);
+
+	/* Start RTC. */
+	writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2);
+	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
+					(tmp & RTCA3_RCR2_START),
+					10, RTCA3_DEFAULT_TIMEOUT_US);
+
+unlock:
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return ret;
+}
+
+static int rtca3_alarm_irq_enable_helper(struct rtca3_priv *priv,
+					 unsigned int enabled)
+{
+	u8 tmp, mask;
+
+	if (enabled) {
+		rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_AF, 0);
+		mask = RTCA3_RCR1_AIE;
+	} else {
+		mask = 0;
+	}
+
+	rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_AIE, mask);
+	return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
+					 ((tmp & RTCA3_RCR1_AIE) == mask),
+					 10, RTCA3_IRQSET_TIMEOUT_US);
+}
+
+static int rtca3_alarm_irq_enable(struct device *dev, unsigned int enabled)
+{
+	struct rtca3_priv *priv = dev_get_drvdata(dev);
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&priv->lock, flags);
+	ret = rtca3_alarm_irq_enable_helper(priv, enabled);
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return ret;
+}
+
+static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{
+	struct rtca3_priv *priv = dev_get_drvdata(dev);
+	u8 sec, min, hour, wday, mday, month;
+	struct rtc_time *tm = &wkalrm->time;
+	unsigned long flags;
+	u32 year100;
+	u16 year;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	sec = readb(priv->base + RTCA3_RSECAR);
+	min = readb(priv->base + RTCA3_RMINAR);
+	hour = readb(priv->base + RTCA3_RHRAR);
+	wday = readb(priv->base + RTCA3_RWKAR);
+	mday = readb(priv->base + RTCA3_RDAYAR);
+	month = readb(priv->base + RTCA3_RMONAR);
+	year = readw(priv->base + RTCA3_RYRAR);
+
+	tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec));
+	tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min));
+	tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour));
+	if (hour & RTCA3_RHRAR_PM)
+		tm->tm_hour += 12;
+	tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday));
+	tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday));
+	tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1;
+	year = FIELD_GET(RTCA3_RYRAR_YR, year);
+	year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20);
+	tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900;
+
+	wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE);
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return 0;
+}
+
+static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{
+	struct rtca3_priv *priv = dev_get_drvdata(dev);
+	struct rtc_time *tm = &wkalrm->time;
+	unsigned long flags;
+	u8 rcr1, tmp;
+	int ret;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	tmp = readb(priv->base + RTCA3_RCR2);
+	if (!(tmp & RTCA3_RCR2_START)) {
+		ret = -EPERM;
+		goto unlock;
+	}
+
+	/* Disable AIE to prevent false interrupts. */
+	rcr1 = readb(priv->base + RTCA3_RCR1);
+	rcr1 &= ~RTCA3_RCR1_AIE;
+	writeb(rcr1, priv->base + RTCA3_RCR1);
+	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
+					!(tmp & RTCA3_RCR1_AIE),
+					10, RTCA3_DEFAULT_TIMEOUT_US);
+	if (ret)
+		goto unlock;
+
+	/* Set the time and enable the alarm. */
+	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR);
+	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR);
+	if (tm->tm_hour > 12) {
+		writeb(RTCA3_AR_ENB | RTCA3_RHRAR_PM | bin2bcd(tm->tm_hour - 12),
+		       priv->base + RTCA3_RHRAR);
+	} else {
+		writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR);
+	}
+	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR);
+	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR);
+	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONAR);
+
+	writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR);
+	writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN);
+
+	/* Make sure we can read back the counters. */
+	rtca3_prepare_cntalrm_regs_for_read(priv, false);
+
+	/* Need to wait for 2 * 1/64 periodic interrupts to be generated. */
+	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT);
+	reinit_completion(&priv->set_alarm_completion);
+
+	/* Enable periodic interrupt. */
+	rcr1 |= RTCA3_RCR1_PIE;
+	writeb(rcr1, priv->base + RTCA3_RCR1);
+	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
+					(tmp & RTCA3_RCR1_PIE),
+					10, RTCA3_IRQSET_TIMEOUT_US);
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	if (ret)
+		goto setup_failed;
+
+	/* Wait for the 2 * 1/64 periodic interrupts. */
+	ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion,
+							msecs_to_jiffies(500));
+	if (ret <= 0) {
+		ret = -ETIMEDOUT;
+		goto setup_failed;
+	}
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	ret = rtca3_alarm_irq_enable_helper(priv, wkalrm->enabled);
+	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
+
+unlock:
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return ret;
+
+setup_failed:
+	spin_lock_irqsave(&priv->lock, flags);
+	/*
+	 * Disable PIE to avoid interrupt storm in case HW needed more than
+	 * specified timeout for setup.
+	 */
+	writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1);
+	readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE),
+				  10, RTCA3_DEFAULT_TIMEOUT_US);
+	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return ret;
+}
+
+static int rtca3_read_offset(struct device *dev, long *offset)
+{
+	struct rtca3_priv *priv = dev_get_drvdata(dev);
+	u8 val, radj, cycles;
+	unsigned long flags;
+	u32 ppb_per_cycle;
+
+	spin_lock_irqsave(&priv->lock, flags);
+	radj = readb(priv->base + RTCA3_RADJ);
+	val = readb(priv->base + RTCA3_RCR2);
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj);
+
+	if (!cycles) {
+		*offset = 0;
+		return 0;
+	}
+
+	if (val & RTCA3_RCR2_ADJP)
+		ppb_per_cycle = priv->ppb.ten_sec;
+	else
+		ppb_per_cycle = priv->ppb.sixty_sec;
+
+	*offset = cycles * ppb_per_cycle;
+	val = FIELD_GET(RTCA3_RADJ_PMADJ, radj);
+	if (val == RTCA3_RADJ_PMADJ_SUB)
+		*offset = -(*offset);
+
+	return 0;
+}
+
+static int rtca3_set_offset(struct device *dev, long offset)
+{
+	struct rtca3_priv *priv = dev_get_drvdata(dev);
+	int cycles, cycles10, cycles60;
+	unsigned long flags;
+	u8 radj, adjp, tmp;
+	int ret;
+
+	/*
+	 * Automatic time error adjustment could be set at intervals of 10
+	 * or 60 seconds.
+	 */
+	cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec);
+	cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec);
+
+	/* We can set b/w 1 and 63 clock cycles. */
+	if (cycles60 >= -RTCA3_RADJ_ADJ_MAX &&
+	    cycles60 <= RTCA3_RADJ_ADJ_MAX) {
+		cycles = cycles60;
+		adjp = 0;
+	} else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX &&
+		   cycles10 <= RTCA3_RADJ_ADJ_MAX) {
+		cycles = cycles10;
+		adjp = RTCA3_RCR2_ADJP;
+	} else {
+		return -ERANGE;
+	}
+
+	radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles));
+	if (!cycles)
+		radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE);
+	else if (cycles > 0)
+		radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD);
+	else
+		radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB);
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	tmp = readb(priv->base + RTCA3_RCR2);
+
+	if ((tmp & RTCA3_RCR2_ADJP) != adjp) {
+		/* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */
+		writeb(0, priv->base + RTCA3_RADJ);
+		ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp,
+						10, RTCA3_DEFAULT_TIMEOUT_US);
+		if (ret)
+			goto unlock;
+
+		rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp);
+		ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
+						((tmp & RTCA3_RCR2_ADJP) == adjp),
+						10, RTCA3_DEFAULT_TIMEOUT_US);
+		if (ret)
+			goto unlock;
+	}
+
+	writeb(radj, priv->base + RTCA3_RADJ);
+	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj),
+					10, RTCA3_DEFAULT_TIMEOUT_US);
+unlock:
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return ret;
+}
+
+static const struct rtc_class_ops rtca3_ops = {
+	.read_time = rtca3_read_time,
+	.set_time = rtca3_set_time,
+	.read_alarm = rtca3_read_alarm,
+	.set_alarm = rtca3_set_alarm,
+	.alarm_irq_enable = rtca3_alarm_irq_enable,
+	.set_offset = rtca3_set_offset,
+	.read_offset = rtca3_read_offset,
+};
+
+static int rtca3_initial_setup(struct rtca3_priv *priv)
+{
+	unsigned long osc32k_rate;
+	u8 pes, tmp, mask;
+	u32 sleep_us;
+	int ret;
+
+	osc32k_rate = clk_get_rate(priv->clk);
+	if (!osc32k_rate)
+		return -EINVAL;
+
+	sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6;
+
+	priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10));
+	priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60));
+
+	/*
+	 * According to HW manual (section 22.4.2. Clock and count mode setting procedure)
+	 * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled.
+	 */
+	usleep_range(sleep_us, sleep_us + 10);
+
+	/* Disable alarm and carry interrupts. */
+	mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE;
+	rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0);
+	ret = readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, !(tmp & mask),
+				 10, RTCA3_DEFAULT_TIMEOUT_US);
+	if (ret)
+		return ret;
+
+	/*
+	 * Stop the RTC and set to 12 hours mode and calendar count mode.
+	 * RCR2.START initial value is undefined so we need to stop here
+	 * all the time.
+	 */
+	mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24 | RTCA3_RCR2_CNTMD;
+	writeb(0, priv->base + RTCA3_RCR2);
+	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
+				 10, RTCA3_DEFAULT_TIMEOUT_US);
+	if (ret)
+		return ret;
+
+	/* Execute reset and wait for reset and calendar count mode to be applied. */
+	mask = RTCA3_RCR2_RESET | RTCA3_RCR2_CNTMD;
+	writeb(RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2);
+	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
+				 10, RTCA3_RESET_TIMEOUT_US);
+	if (ret)
+		return ret;
+
+	/*
+	 * According to HW manual (section 22.6.3. Notes on writing to and reading
+	 * from registers) after reset we need to wait 6 clock cycles before
+	 * writing to RTC registers.
+	 */
+	usleep_range(sleep_us, sleep_us + 10);
+
+	/* Set no adjustment. */
+	writeb(0, priv->base + RTCA3_RADJ);
+	ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10,
+				 RTCA3_DEFAULT_TIMEOUT_US);
+
+	/* Start the RTC and enable automatic time error adjustment. */
+	mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE;
+	writeb(RTCA3_RCR2_START | RTCA3_RCR2_AADJE, priv->base + RTCA3_RCR2);
+	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask),
+				 10, RTCA3_START_TIMEOUT_US);
+	if (ret)
+		return ret;
+
+	/*
+	 * According to HW manual (section 22.6.4. Notes on writing to and reading
+	 * from registers) we need to wait 1/128 seconds while the clock is operating
+	 * (RCR2.START bit = 1) to be able to read the counters after a return from
+	 * reset.
+	 */
+	usleep_range(8000, 9000);
+
+	/* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */
+	pes = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC);
+	rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, pes);
+	return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == pes),
+				  10, RTCA3_DEFAULT_TIMEOUT_US);
+}
+
+static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv)
+{
+	struct device *dev = &pdev->dev;
+	int ret, irq;
+
+	irq = platform_get_irq_byname(pdev, "alarm");
+	if (irq < 0)
+		return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n");
+
+	ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n");
+	priv->wakeup_irq = irq;
+
+	irq = platform_get_irq_byname(pdev, "period");
+	if (irq < 0)
+		return dev_err_probe(dev, irq, "Failed to get period IRQ!\n");
+
+	ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to request period IRQ!\n");
+
+	/*
+	 * Driver doesn't implement carry handler. Just get the IRQ here
+	 * for backward compatibility, in case carry support will be added later.
+	 */
+	irq = platform_get_irq_byname(pdev, "carry");
+	if (irq < 0)
+		return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n");
+
+	return 0;
+}
+
+static int rtca3_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rtca3_priv *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	priv->clk = devm_clk_get_enabled(dev, "counter");
+	if (IS_ERR(priv->clk))
+		return PTR_ERR(priv->clk);
+
+	platform_set_drvdata(pdev, priv);
+
+	spin_lock_init(&priv->lock);
+	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
+	init_completion(&priv->set_alarm_completion);
+
+	ret = rtca3_initial_setup(priv);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to setup the RTC!\n");
+
+	ret = rtca3_request_irqs(pdev, priv);
+	if (ret)
+		return ret;
+
+	device_init_wakeup(&pdev->dev, 1);
+
+	priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
+	if (IS_ERR(priv->rtc_dev))
+		return PTR_ERR(priv->rtc_dev);
+
+	priv->rtc_dev->ops = &rtca3_ops;
+	priv->rtc_dev->max_user_freq = 256;
+	priv->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0);
+	priv->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59);
+
+	return devm_rtc_register_device(priv->rtc_dev);
+}
+
+static void rtca3_remove(struct platform_device *pdev)
+{
+	struct rtca3_priv *priv = platform_get_drvdata(pdev);
+	u8 tmp, mask = RTCA3_RCR1_AIE | RTCA3_RCR1_PIE;
+	unsigned long flags;
+
+	spin_lock_irqsave(&priv->lock, flags);
+
+	/* Disable alarm, periodic interrupt. */
+	rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0);
+	readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & mask),
+				  10, RTCA3_IRQSET_TIMEOUT_US);
+
+	spin_unlock_irqrestore(&priv->lock, flags);
+}
+
+static int __maybe_unused rtca3_suspend(struct device *dev)
+{
+	struct rtca3_priv *priv = dev_get_drvdata(dev);
+
+	if (!device_may_wakeup(dev))
+		return 0;
+
+	/* Alarm setup in progress. */
+	if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE)
+		return -EBUSY;
+
+	enable_irq_wake(priv->wakeup_irq);
+
+	return 0;
+}
+
+static int rtca3_clean_alarm(struct rtca3_priv *priv)
+{
+	struct rtc_device *rtc_dev = priv->rtc_dev;
+	time64_t alarm_time, now;
+	struct rtc_wkalrm alarm;
+	unsigned long flags;
+	struct rtc_time tm;
+	u8 pending;
+	int ret;
+
+	ret = rtc_read_alarm(rtc_dev, &alarm);
+	if (ret)
+		return ret;
+
+	if (!alarm.enabled)
+		return 0;
+
+	ret = rtc_read_time(rtc_dev, &tm);
+	if (ret)
+		return ret;
+
+	alarm_time = rtc_tm_to_time64(&alarm.time);
+	now = rtc_tm_to_time64(&tm);
+	if (alarm_time >= now)
+		return 0;
+
+	/*
+	 * Heuristically, it has been determined that when returning from deep
+	 * sleep state the RTCA3_RSR.AF is zero even though the alarm expired.
+	 * Call again the rtc_update_irq() if alarm helper detects this.
+	 */
+
+	spin_lock_irqsave(&priv->lock, flags);
+	pending = rtca3_alarm_handler_helper(priv);
+	if (!pending)
+		rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF);
+	spin_unlock_irqrestore(&priv->lock, flags);
+
+	return 0;
+}
+
+static int __maybe_unused rtca3_resume(struct device *dev)
+{
+	struct rtca3_priv *priv = dev_get_drvdata(dev);
+
+	if (!device_may_wakeup(dev))
+		return 0;
+
+	disable_irq_wake(priv->wakeup_irq);
+
+	/*
+	 * According to the HW manual (section 22.6.4 Notes on writing to
+	 * and reading from registers) we need to wait 1/128 seconds while
+	 * RCR2.START = 1 to be able to read the counters after a return from low
+	 * power consumption state.
+	 */
+	mdelay(8);
+
+	/*
+	 * The alarm cannot wake the system from deep sleep states. In case
+	 * we return from deep sleep states and the alarm expired we need
+	 * to disable it to avoid failures when setting another alarm.
+	 */
+	return rtca3_clean_alarm(priv);
+}
+
+static SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume);
+
+static const struct of_device_id rtca3_of_match[] = {
+	{ .compatible = "renesas,rzg3s-rtc", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rtca3_of_match);
+
+static struct platform_driver rtca3_platform_driver = {
+	.driver = {
+		.name = "rtc-rtca3",
+		.pm = &rtca3_pm_ops,
+		.of_match_table = rtca3_of_match,
+	},
+	.probe = rtca3_probe,
+	.remove_new = rtca3_remove,
+};
+module_platform_driver(rtca3_platform_driver);
+
+MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver");
+MODULE_AUTHOR("Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>");
+MODULE_LICENSE("GPL");
-- 
2.39.2

[PATCH 07/12] arm64: dts: renesas: r9a08g045: Add VBATTB node

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add the DT node for the VBATTB IP along with DT bindings for the clock
it provides.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 32 ++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 2162c247d6de..b7bd2e1f3462 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -72,6 +72,31 @@ scif0: serial@1004b800 {
 			status = "disabled";
 		};
 
+		vbattb: vbattb@1005c000 {
+			compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
+			reg = <0 0x1005c000 0 0x1000>;
+			ranges = <0 0 0 0x1005c000 0 0x1000>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "tampdi";
+			clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
+			clock-names = "bclk";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G045_VBAT_BRESETN>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			vbattclk: clock-controller@1c {
+				compatible = "renesas,rzg3s-vbattb-clk";
+				reg = <0 0x1c 0 0x10>;
+				clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
+				clock-names = "bclk", "vbattb_xtal";
+				#clock-cells = <0>;
+				power-domains = <&cpg>;
+				status = "disabled";
+			};
+		};
+
 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a08g045-cpg";
 			reg = <0 0x11010000 0 0x10000>;
@@ -296,4 +321,11 @@ timer {
 				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 	};
+
+	vbattb_xtal: vbattb-xtal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board. */
+		clock-frequency = <0>;
+	};
 };
-- 
2.39.2

[PATCH 08/12] arm64: dts: renesas: r9a08g045: Add RTC node

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index b7bd2e1f3462..88a20c954ca6 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -72,6 +72,18 @@ scif0: serial@1004b800 {
 			status = "disabled";
 		};
 
+		rtc: rtc@1004ec00 {
+			compatible = "renesas,rzg3s-rtc";
+			reg = <0 0x1004ec00 0 0x400>;
+			interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "alarm", "period", "carry";
+			clocks = <&vbattclk>;
+			clock-names = "counter";
+			status = "disabled";
+		};
+
 		vbattb: vbattb@1005c000 {
 			compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
 			reg = <0 0x1005c000 0 0x1000>;
-- 
2.39.2

[PATCH 09/12] arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB clock

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable the VBATTB clock controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 8a3d302f1535..517ce275916a 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -341,6 +341,19 @@ mux {
 	};
 };
 
+&vbattb_xtal {
+	clock-frequency = <32768>;
+};
+
+&vbattb {
+	status = "okay";
+};
+
+&vbattclk {
+	renesas,vbattb-load-nanofarads = <12500>;
+	status = "okay";
+};
+
 &wdt0 {
 	timeout-sec = <60>;
 	status = "okay";
-- 
2.39.2

[PATCH 10/12] arm64: dts: renesas: rzg3s-smarc-som: Enable RTC

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable RTC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index 517ce275916a..82a80fd8e7ec 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -341,6 +341,10 @@ mux {
 	};
 };
 
+&rtc {
+	status = "okay";
+};
+
 &vbattb_xtal {
 	clock-frequency = <32768>;
 };
-- 
2.39.2

[PATCH 11/12] arm64: defconfig: Enable VBATTB clock flag

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable VBATTB clock driver flag (CONFIG_CLK_VBATTB).

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 05abba0a0209..fcb0c7ee8769 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1348,6 +1348,7 @@ CONFIG_SM_VIDEOCC_8250=y
 CONFIG_QCOM_HFPLL=y
 CONFIG_CLK_GFM_LPASS_SM8250=m
 CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
+CONFIG_CLK_VBATTB=y
 CONFIG_HWSPINLOCK=y
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_TEGRA186_TIMER=y
-- 
2.39.2

[PATCH 12/12] arm64: defconfig: Enable Renesas RTCA-3 flag

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Enable Renesas RTCA-3 flag for the Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index fcb0c7ee8769..86e74da7a9c9 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1202,6 +1202,7 @@ CONFIG_RTC_DRV_IMX_SC=m
 CONFIG_RTC_DRV_MT6397=m
 CONFIG_RTC_DRV_XGENE=y
 CONFIG_RTC_DRV_TI_K3=m
+CONFIG_RTC_DRV_RENESAS_RTCA3=y
 CONFIG_DMADEVICES=y
 CONFIG_DMA_BCM2835=y
 CONFIG_DMA_SUN6I=m
-- 
2.39.2

RE: [PATCH 06/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC

[Biju Das]

Hi Claudiu,

Thanks for the patch.

> -----Original Message-----
> From: Claudiu <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 14, 2024 8:19 AM
> Subject: [PATCH 06/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> The RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC has calendar count mode and binary count
> mode (selectable though RCR2.CNTMD) capabilities, alarm capabilities, clock error correction
> capabilities. It can generate alarm, period, carry interrupts.
> 
> Add a driver for RTCA-3 IP. The driver implements calendar count mode (as the conversion b/w RTC
> and system time is simpler, done with bcd2bin(), bin2bcd()), read and set time, read and set alarm,
> read and set an offset.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  MAINTAINERS                     |   8 +
>  drivers/rtc/Kconfig             |  10 +
>  drivers/rtc/Makefile            |   1 +
>  drivers/rtc/rtc-renesas-rtca3.c | 891 ++++++++++++++++++++++++++++++++
>  4 files changed, 910 insertions(+)
>  create mode 100644 drivers/rtc/rtc-renesas-rtca3.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 670b8201973b..0b4bf350c416 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19173,6 +19173,14 @@ S:	Supported
>  F:	Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
>  F:	drivers/counter/rz-mtu3-cnt.c
> 
> +RENESAS RZ/G3S RTC DRIVER
Maybe make it generic "RENESAS RTCA3 RTC DRIVER" as it is an IP
can be used in future SoCs??

> +M:	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> +L:	linux-rtc@vger.kernel.org
> +L:	linux-renesas-soc@vger.kernel.org
> +S:	Supported
> +F:	Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
Make generic name "renesas,rtca3-rtc.yaml??

Cheers,
Biju

> +F:	drivers/rtc/rtc-renesas-rtca3.c
> +
>  RENESAS RZ/N1 A5PSW SWITCH DRIVER
>  M:	Clément Léger <clement.leger@bootlin.com>
>  L:	linux-renesas-soc@vger.kernel.org
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2a95b05982ad..3b29b35e48e0 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -1978,6 +1978,16 @@ config RTC_DRV_MA35D1
>  	   This driver can also be built as a module, if so, the module
>  	   will be called "rtc-ma35d1".
> 
> +config RTC_DRV_RENESAS_RTCA3
> +	tristate "Renesas RTCA-3 RTC"
> +	depends on ARCH_RENESAS
> +	help
> +	  If you say yes here you get support for the Renesas RTCA-3 RTC
> +	  available on the Renesas RZ/G3S SoC.
> +
> +	  This driver can also be built as a module, if so, the module
> +	  will be called "rtc-rtca3".
> +
>  comment "HID Sensor RTC drivers"
> 
>  config RTC_DRV_HID_SENSOR_TIME
> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 3004e372f25f..52844f13b247 100644
> --- a/drivers/rtc/Makefile
> +++ b/drivers/rtc/Makefile
> @@ -157,6 +157,7 @@ obj-$(CONFIG_RTC_DRV_RX8025)	+= rtc-rx8025.o
>  obj-$(CONFIG_RTC_DRV_RX8111)	+= rtc-rx8111.o
>  obj-$(CONFIG_RTC_DRV_RX8581)	+= rtc-rx8581.o
>  obj-$(CONFIG_RTC_DRV_RZN1)	+= rtc-rzn1.o
> +obj-$(CONFIG_RTC_DRV_RENESAS_RTCA3)	+= rtc-renesas-rtca3.o
>  obj-$(CONFIG_RTC_DRV_S35390A)	+= rtc-s35390a.o
>  obj-$(CONFIG_RTC_DRV_S3C)	+= rtc-s3c.o
>  obj-$(CONFIG_RTC_DRV_S5M)	+= rtc-s5m.o
> diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c new file mode 100644
> index 000000000000..e2edf12d0c54
> --- /dev/null
> +++ b/drivers/rtc/rtc-renesas-rtca3.c
> @@ -0,0 +1,891 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * On-Chip RTC Support available on RZ/G3S SoC
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +#include <linux/bcd.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/iopoll.h>
> +#include <linux/interrupt.h>
> +#include <linux/jiffies.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/rtc.h>
> +
> +/* Counter registers. */
> +#define RTCA3_RSECCNT			0x2
> +#define RTCA3_RSECCNT_SEC		GENMASK(6, 0)
> +#define RTCA3_RMINCNT			0x4
> +#define RTCA3_RMINCNT_MIN		GENMASK(6, 0)
> +#define RTCA3_RHRCNT			0x6
> +#define RTCA3_RHRCNT_HR			GENMASK(5, 0)
> +#define RTCA3_RHRCNT_PM			BIT(6)
> +#define RTCA3_RWKCNT			0x8
> +#define RTCA3_RWKCNT_WK			GENMASK(2, 0)
> +#define RTCA3_RDAYCNT			0xa
> +#define RTCA3_RDAYCNT_DAY		GENMASK(5, 0)
> +#define RTCA3_RMONCNT			0xc
> +#define RTCA3_RMONCNT_MONTH		GENMASK(4, 0)
> +#define RTCA3_RYRCNT			0xe
> +#define RTCA3_RYRCNT_YEAR		GENMASK(7, 0)
> +
> +/* Alarm registers. */
> +#define RTCA3_RSECAR			0x10
> +#define RTCA3_RSECAR_SEC		GENMASK(6, 0)
> +#define RTCA3_RMINAR			0x12
> +#define RTCA3_RMINAR_MIN		GENMASK(6, 0)
> +#define RTCA3_RHRAR			0x14
> +#define RTCA3_RHRAR_HR			GENMASK(5, 0)
> +#define RTCA3_RHRAR_PM			BIT(6)
> +#define RTCA3_RWKAR			0x16
> +#define RTCA3_RWKAR_DAYW		GENMASK(2, 0)
> +#define RTCA3_RDAYAR			0x18
> +#define RTCA3_RDAYAR_DATE		GENMASK(5, 0)
> +#define RTCA3_RMONAR			0x1a
> +#define RTCA3_RMONAR_MON		GENMASK(4, 0)
> +#define RTCA3_RYRAR			0x1c
> +#define RTCA3_RYRAR_YR			GENMASK(7, 0)
> +#define RTCA3_RYRAREN			0x1e
> +
> +/* Alarm enable bit (for all alarm registers). */
> +#define RTCA3_AR_ENB			BIT(7)
> +
> +/* Control registers. */
> +#define RTCA3_RCR1			0x22
> +#define RTCA3_RCR1_AIE			BIT(0)
> +#define RTCA3_RCR1_CIE			BIT(1)
> +#define RTCA3_RCR1_PIE			BIT(2)
> +#define RTCA3_RCR1_PES			GENMASK(7, 4)
> +#define RTCA3_RCR1_PES_1_64_SEC		0x8
> +#define RTCA3_RCR2			0x24
> +#define RTCA3_RCR2_START		BIT(0)
> +#define RTCA3_RCR2_RESET		BIT(1)
> +#define RTCA3_RCR2_AADJE		BIT(4)
> +#define RTCA3_RCR2_ADJP			BIT(5)
> +#define RTCA3_RCR2_HR24			BIT(6)
> +#define RTCA3_RCR2_CNTMD		BIT(7)
> +#define RTCA3_RSR			0x20
> +#define RTCA3_RSR_AF			BIT(0)
> +#define RTCA3_RSR_CF			BIT(1)
> +#define RTCA3_RSR_PF			BIT(2)
> +#define RTCA3_RADJ			0x2e
> +#define RTCA3_RADJ_ADJ			GENMASK(5, 0)
> +#define RTCA3_RADJ_ADJ_MAX		0x3f
> +#define RTCA3_RADJ_PMADJ		GENMASK(7, 6)
> +#define RTCA3_RADJ_PMADJ_NONE		0
> +#define RTCA3_RADJ_PMADJ_ADD		1
> +#define RTCA3_RADJ_PMADJ_SUB		2
> +
> +/* Polling operation timeouts. */
> +#define RTCA3_DEFAULT_TIMEOUT_US	150
> +#define RTCA3_IRQSET_TIMEOUT_US		5000
> +#define RTCA3_START_TIMEOUT_US		150000
> +#define RTCA3_RESET_TIMEOUT_US		200000
> +
> +/**
> + * enum rtca3_alrm_set_step - RTCA3 alarm set steps
> + * @RTCA3_ALRM_SSTEP_DONE: alarm setup done step
> + * @RTCA3_ALRM_SSTEP_IRQ: two 1/64 periodic IRQs were generated step
> + * @RTCA3_ALRM_SSTEP_INIT: alarm setup initialization step  */ enum
> +rtca3_alrm_set_step {
> +	RTCA3_ALRM_SSTEP_DONE = 0,
> +	RTCA3_ALRM_SSTEP_IRQ = 1,
> +	RTCA3_ALRM_SSTEP_INIT = 3,
> +};
> +
> +/**
> + * struct rtca3_ppb_per_cycle - PPB per cycle
> + * @ten_sec: PPB per cycle in 10 seconds adjutment mode
> + * @sixty_sec: PPB per cycle in 60 seconds adjustment mode  */ struct
> +rtca3_ppb_per_cycle {
> +	int ten_sec;
> +	int sixty_sec;
> +};
> +
> +/**
> + * struct rtca3_priv - RTCA3 private data structure
> + * @base: base address
> + * @clk: RTC clock
> + * @rtc_dev: RTC device
> + * @set_alarm_completion: alarm setup completion
> + * @alrm_sstep: alarm setup step (see enum rtca3_alrm_set_step)
> + * @lock: device lock
> + * @ppb: ppb per cycle for each the available adjustment modes
> + * @wakeup_irq: wakeup IRQ
> + */
> +struct rtca3_priv {
> +	void __iomem *base;
> +	struct clk *clk;
> +	struct rtc_device *rtc_dev;
> +	struct completion set_alarm_completion;
> +	atomic_t alrm_sstep;
> +	spinlock_t lock;
> +	struct rtca3_ppb_per_cycle ppb;
> +	int wakeup_irq;
> +};
> +
> +static void rtca3_byte_update_bits(struct rtca3_priv *priv, u8 off, u8
> +mask, u8 val) {
> +	u8 tmp;
> +
> +	tmp = readb(priv->base + off);
> +	tmp &= ~(mask);
> +	tmp |= (val & mask);
> +	writeb(tmp, priv->base + off);
> +}
> +
> +static u8 rtca3_alarm_handler_helper(struct rtca3_priv *priv) {
> +	u8 val, pending;
> +
> +	val = readb(priv->base + RTCA3_RSR);
> +	pending = val & RTCA3_RSR_AF;
> +	writeb(val & ~pending, priv->base + RTCA3_RSR);
> +
> +	if (pending)
> +		rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF);
> +
> +	return pending;
> +}
> +
> +static irqreturn_t rtca3_alarm_handler(int irq, void *dev_id) {
> +	struct rtca3_priv *priv = dev_id;
> +	u8 pending;
> +
> +	spin_lock(&priv->lock);
> +	pending = rtca3_alarm_handler_helper(priv);
> +	spin_unlock(&priv->lock);
> +
> +	return IRQ_RETVAL(pending);
> +}
> +
> +static irqreturn_t rtca3_periodic_handler(int irq, void *dev_id) {
> +	struct rtca3_priv *priv = dev_id;
> +	u8 val, pending;
> +
> +	spin_lock(&priv->lock);
> +
> +	val = readb(priv->base + RTCA3_RSR);
> +	pending = val & RTCA3_RSR_PF;
> +
> +	if (pending) {
> +		writeb(val & ~pending, priv->base + RTCA3_RSR);
> +
> +		if (atomic_read(&priv->alrm_sstep) > RTCA3_ALRM_SSTEP_IRQ) {
> +			/* Alarm setup in progress. */
> +			atomic_dec(&priv->alrm_sstep);
> +
> +			if (atomic_read(&priv->alrm_sstep) == RTCA3_ALRM_SSTEP_IRQ) {
> +				/*
> +				 * We got 2 * 1/64 periodic interrupts. Disable
> +				 * interrupt and let alarm setup continue.
> +				 */
> +				rtca3_byte_update_bits(priv, RTCA3_RCR1,
> +						       RTCA3_RCR1_PIE, 0);
> +				readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, val,
> +							  !(val & RTCA3_RCR1_PIE),
> +							  10, RTCA3_DEFAULT_TIMEOUT_US);
> +				complete(&priv->set_alarm_completion);
> +			}
> +		}
> +	}
> +
> +	spin_unlock(&priv->lock);
> +
> +	return IRQ_RETVAL(pending);
> +}
> +
> +static void rtca3_prepare_cntalrm_regs_for_read(struct rtca3_priv
> +*priv, bool cnt) {
> +	/* Offset b/w time and alarm registers. */
> +	u8 offset = cnt ? 0 : 0xe;
> +
> +	/*
> +	 * According to HW manual (section 22.6.4. Notes on writing to and
> +	 * reading from registers) after writing to count registers, alarm
> +	 * registers, year alarm enable register, bits RCR2.AADJE, AADJP,
> +	 * and HR24 register, we need to do 3 empty reads before being
> +	 * able to fetch the registers content.
> +	 */
> +	for (u8 i = 0; i < 3; i++) {
> +		readb(priv->base + RTCA3_RSECCNT + offset);
> +		readb(priv->base + RTCA3_RMINCNT + offset);
> +		readb(priv->base + RTCA3_RHRCNT  + offset);
> +		readb(priv->base + RTCA3_RWKCNT  + offset);
> +		readb(priv->base + RTCA3_RDAYCNT + offset);
> +		readw(priv->base + RTCA3_RYRCNT  + offset);
> +		if (!cnt)
> +			readb(priv->base + RTCA3_RYRAREN);
> +	}
> +}
> +
> +static int rtca3_read_time(struct device *dev, struct rtc_time *tm) {
> +	struct rtca3_priv *priv = dev_get_drvdata(dev);
> +	u8 sec, min, hour, wday, mday, month, tmp;
> +	unsigned long flags;
> +	u8 trials = 0;
> +	int ret = 0;
> +	u32 year100;
> +	u16 year;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	tmp = readb(priv->base + RTCA3_RCR2);
> +	if (!(tmp & RTCA3_RCR2_START)) {
> +		ret = -EINVAL;
> +		goto unlock;
> +	}
> +
> +	do {
> +		/* Clear carry interrupt. */
> +		rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_CF, 0);
> +
> +		/* Read counters. */
> +		sec = readb(priv->base + RTCA3_RSECCNT);
> +		min = readb(priv->base + RTCA3_RMINCNT);
> +		hour = readb(priv->base + RTCA3_RHRCNT);
> +		wday = readb(priv->base + RTCA3_RWKCNT);
> +		mday = readb(priv->base + RTCA3_RDAYCNT);
> +		month = readb(priv->base + RTCA3_RMONCNT);
> +		year = readw(priv->base + RTCA3_RYRCNT);
> +
> +		tmp = readb(priv->base + RTCA3_RSR);
> +
> +		/*
> +		 * We cannot generate carries due to reading 64Hz counter as
> +		 * the driver doesn't implement carry, thus, carries will be
> +		 * generated once per seconds. Add a timeout of 5 trials here
> +		 * to avoid infinite loop, if any.
> +		 */
> +	} while ((tmp & RTCA3_RSR_CF) && ++trials < 5);
> +
> +	if (trials >= 5) {
> +		ret = -ETIMEDOUT;
> +		goto unlock;
> +	}
> +
> +	tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECCNT_SEC, sec));
> +	tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINCNT_MIN, min));
> +	tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRCNT_HR, hour));
> +	if (hour & RTCA3_RHRCNT_PM)
> +		tm->tm_hour += 12;
> +	tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKCNT_WK, wday));
> +	tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYCNT_DAY, mday));
> +	tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONCNT_MONTH, month)) - 1;
> +	year = FIELD_GET(RTCA3_RYRCNT_YEAR, year);
> +	year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20);
> +	tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900;
> +
> +unlock:
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	return ret;
> +}
> +
> +static int rtca3_set_time(struct device *dev, struct rtc_time *tm) {
> +	struct rtca3_priv *priv = dev_get_drvdata(dev);
> +	unsigned long flags;
> +	u8 rcr2, tmp;
> +	int ret;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	/* Stop the RTC. */
> +	rcr2 = readb(priv->base + RTCA3_RCR2);
> +	writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2);
> +	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
> +					!(tmp & RTCA3_RCR2_START),
> +					10, RTCA3_DEFAULT_TIMEOUT_US);
> +	if (ret)
> +		goto unlock;
> +
> +	/* Update time. */
> +	writeb(bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECCNT);
> +	writeb(bin2bcd(tm->tm_min), priv->base + RTCA3_RMINCNT);
> +	if (tm->tm_hour > 12)
> +		writeb(RTCA3_RHRCNT_PM | bin2bcd(tm->tm_hour - 12), priv->base + RTCA3_RHRCNT);
> +	else
> +		writeb(bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRCNT);
> +	writeb(bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKCNT);
> +	writeb(bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYCNT);
> +	writeb(bin2bcd(tm->tm_mon + 1), priv->base + RTCA3_RMONCNT);
> +	writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRCNT);
> +
> +	/* Make sure we can read back the counters. */
> +	rtca3_prepare_cntalrm_regs_for_read(priv, true);
> +
> +	/* Start RTC. */
> +	writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2);
> +	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
> +					(tmp & RTCA3_RCR2_START),
> +					10, RTCA3_DEFAULT_TIMEOUT_US);
> +
> +unlock:
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	return ret;
> +}
> +
> +static int rtca3_alarm_irq_enable_helper(struct rtca3_priv *priv,
> +					 unsigned int enabled)
> +{
> +	u8 tmp, mask;
> +
> +	if (enabled) {
> +		rtca3_byte_update_bits(priv, RTCA3_RSR, RTCA3_RSR_AF, 0);
> +		mask = RTCA3_RCR1_AIE;
> +	} else {
> +		mask = 0;
> +	}
> +
> +	rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_AIE, mask);
> +	return readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
> +					 ((tmp & RTCA3_RCR1_AIE) == mask),
> +					 10, RTCA3_IRQSET_TIMEOUT_US);
> +}
> +
> +static int rtca3_alarm_irq_enable(struct device *dev, unsigned int
> +enabled) {
> +	struct rtca3_priv *priv = dev_get_drvdata(dev);
> +	unsigned long flags;
> +	int ret;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +	ret = rtca3_alarm_irq_enable_helper(priv, enabled);
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	return ret;
> +}
> +
> +static int rtca3_read_alarm(struct device *dev, struct rtc_wkalrm
> +*wkalrm) {
> +	struct rtca3_priv *priv = dev_get_drvdata(dev);
> +	u8 sec, min, hour, wday, mday, month;
> +	struct rtc_time *tm = &wkalrm->time;
> +	unsigned long flags;
> +	u32 year100;
> +	u16 year;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	sec = readb(priv->base + RTCA3_RSECAR);
> +	min = readb(priv->base + RTCA3_RMINAR);
> +	hour = readb(priv->base + RTCA3_RHRAR);
> +	wday = readb(priv->base + RTCA3_RWKAR);
> +	mday = readb(priv->base + RTCA3_RDAYAR);
> +	month = readb(priv->base + RTCA3_RMONAR);
> +	year = readw(priv->base + RTCA3_RYRAR);
> +
> +	tm->tm_sec = bcd2bin(FIELD_GET(RTCA3_RSECAR_SEC, sec));
> +	tm->tm_min = bcd2bin(FIELD_GET(RTCA3_RMINAR_MIN, min));
> +	tm->tm_hour = bcd2bin(FIELD_GET(RTCA3_RHRAR_HR, hour));
> +	if (hour & RTCA3_RHRAR_PM)
> +		tm->tm_hour += 12;
> +	tm->tm_wday = bcd2bin(FIELD_GET(RTCA3_RWKAR_DAYW, wday));
> +	tm->tm_mday = bcd2bin(FIELD_GET(RTCA3_RDAYAR_DATE, mday));
> +	tm->tm_mon = bcd2bin(FIELD_GET(RTCA3_RMONAR_MON, month)) - 1;
> +	year = FIELD_GET(RTCA3_RYRAR_YR, year);
> +	year100 = bcd2bin((year == 0x99) ? 0x19 : 0x20);
> +	tm->tm_year = (year100 * 100 + bcd2bin(year)) - 1900;
> +
> +	wkalrm->enabled = !!(readb(priv->base + RTCA3_RCR1) & RTCA3_RCR1_AIE);
> +
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int rtca3_set_alarm(struct device *dev, struct rtc_wkalrm
> +*wkalrm) {
> +	struct rtca3_priv *priv = dev_get_drvdata(dev);
> +	struct rtc_time *tm = &wkalrm->time;
> +	unsigned long flags;
> +	u8 rcr1, tmp;
> +	int ret;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	tmp = readb(priv->base + RTCA3_RCR2);
> +	if (!(tmp & RTCA3_RCR2_START)) {
> +		ret = -EPERM;
> +		goto unlock;
> +	}
> +
> +	/* Disable AIE to prevent false interrupts. */
> +	rcr1 = readb(priv->base + RTCA3_RCR1);
> +	rcr1 &= ~RTCA3_RCR1_AIE;
> +	writeb(rcr1, priv->base + RTCA3_RCR1);
> +	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
> +					!(tmp & RTCA3_RCR1_AIE),
> +					10, RTCA3_DEFAULT_TIMEOUT_US);
> +	if (ret)
> +		goto unlock;
> +
> +	/* Set the time and enable the alarm. */
> +	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_sec), priv->base + RTCA3_RSECAR);
> +	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_min), priv->base + RTCA3_RMINAR);
> +	if (tm->tm_hour > 12) {
> +		writeb(RTCA3_AR_ENB | RTCA3_RHRAR_PM | bin2bcd(tm->tm_hour - 12),
> +		       priv->base + RTCA3_RHRAR);
> +	} else {
> +		writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_hour), priv->base + RTCA3_RHRAR);
> +	}
> +	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_wday), priv->base + RTCA3_RWKAR);
> +	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mday), priv->base + RTCA3_RDAYAR);
> +	writeb(RTCA3_AR_ENB | bin2bcd(tm->tm_mon + 1), priv->base +
> +RTCA3_RMONAR);
> +
> +	writew(bin2bcd(tm->tm_year % 100), priv->base + RTCA3_RYRAR);
> +	writeb(RTCA3_AR_ENB, priv->base + RTCA3_RYRAREN);
> +
> +	/* Make sure we can read back the counters. */
> +	rtca3_prepare_cntalrm_regs_for_read(priv, false);
> +
> +	/* Need to wait for 2 * 1/64 periodic interrupts to be generated. */
> +	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_INIT);
> +	reinit_completion(&priv->set_alarm_completion);
> +
> +	/* Enable periodic interrupt. */
> +	rcr1 |= RTCA3_RCR1_PIE;
> +	writeb(rcr1, priv->base + RTCA3_RCR1);
> +	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp,
> +					(tmp & RTCA3_RCR1_PIE),
> +					10, RTCA3_IRQSET_TIMEOUT_US);
> +
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	if (ret)
> +		goto setup_failed;
> +
> +	/* Wait for the 2 * 1/64 periodic interrupts. */
> +	ret = wait_for_completion_interruptible_timeout(&priv->set_alarm_completion,
> +							msecs_to_jiffies(500));
> +	if (ret <= 0) {
> +		ret = -ETIMEDOUT;
> +		goto setup_failed;
> +	}
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	ret = rtca3_alarm_irq_enable_helper(priv, wkalrm->enabled);
> +	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
> +
> +unlock:
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	return ret;
> +
> +setup_failed:
> +	spin_lock_irqsave(&priv->lock, flags);
> +	/*
> +	 * Disable PIE to avoid interrupt storm in case HW needed more than
> +	 * specified timeout for setup.
> +	 */
> +	writeb(rcr1 & ~RTCA3_RCR1_PIE, priv->base + RTCA3_RCR1);
> +	readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & ~RTCA3_RCR1_PIE),
> +				  10, RTCA3_DEFAULT_TIMEOUT_US);
> +	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	return ret;
> +}
> +
> +static int rtca3_read_offset(struct device *dev, long *offset) {
> +	struct rtca3_priv *priv = dev_get_drvdata(dev);
> +	u8 val, radj, cycles;
> +	unsigned long flags;
> +	u32 ppb_per_cycle;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +	radj = readb(priv->base + RTCA3_RADJ);
> +	val = readb(priv->base + RTCA3_RCR2);
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	cycles = FIELD_GET(RTCA3_RADJ_ADJ, radj);
> +
> +	if (!cycles) {
> +		*offset = 0;
> +		return 0;
> +	}
> +
> +	if (val & RTCA3_RCR2_ADJP)
> +		ppb_per_cycle = priv->ppb.ten_sec;
> +	else
> +		ppb_per_cycle = priv->ppb.sixty_sec;
> +
> +	*offset = cycles * ppb_per_cycle;
> +	val = FIELD_GET(RTCA3_RADJ_PMADJ, radj);
> +	if (val == RTCA3_RADJ_PMADJ_SUB)
> +		*offset = -(*offset);
> +
> +	return 0;
> +}
> +
> +static int rtca3_set_offset(struct device *dev, long offset) {
> +	struct rtca3_priv *priv = dev_get_drvdata(dev);
> +	int cycles, cycles10, cycles60;
> +	unsigned long flags;
> +	u8 radj, adjp, tmp;
> +	int ret;
> +
> +	/*
> +	 * Automatic time error adjustment could be set at intervals of 10
> +	 * or 60 seconds.
> +	 */
> +	cycles10 = DIV_ROUND_CLOSEST(offset, priv->ppb.ten_sec);
> +	cycles60 = DIV_ROUND_CLOSEST(offset, priv->ppb.sixty_sec);
> +
> +	/* We can set b/w 1 and 63 clock cycles. */
> +	if (cycles60 >= -RTCA3_RADJ_ADJ_MAX &&
> +	    cycles60 <= RTCA3_RADJ_ADJ_MAX) {
> +		cycles = cycles60;
> +		adjp = 0;
> +	} else if (cycles10 >= -RTCA3_RADJ_ADJ_MAX &&
> +		   cycles10 <= RTCA3_RADJ_ADJ_MAX) {
> +		cycles = cycles10;
> +		adjp = RTCA3_RCR2_ADJP;
> +	} else {
> +		return -ERANGE;
> +	}
> +
> +	radj = FIELD_PREP(RTCA3_RADJ_ADJ, abs(cycles));
> +	if (!cycles)
> +		radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_NONE);
> +	else if (cycles > 0)
> +		radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_ADD);
> +	else
> +		radj |= FIELD_PREP(RTCA3_RADJ_PMADJ, RTCA3_RADJ_PMADJ_SUB);
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	tmp = readb(priv->base + RTCA3_RCR2);
> +
> +	if ((tmp & RTCA3_RCR2_ADJP) != adjp) {
> +		/* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */
> +		writeb(0, priv->base + RTCA3_RADJ);
> +		ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, !tmp,
> +						10, RTCA3_DEFAULT_TIMEOUT_US);
> +		if (ret)
> +			goto unlock;
> +
> +		rtca3_byte_update_bits(priv, RTCA3_RCR2, RTCA3_RCR2_ADJP, adjp);
> +		ret = readb_poll_timeout_atomic(priv->base + RTCA3_RCR2, tmp,
> +						((tmp & RTCA3_RCR2_ADJP) == adjp),
> +						10, RTCA3_DEFAULT_TIMEOUT_US);
> +		if (ret)
> +			goto unlock;
> +	}
> +
> +	writeb(radj, priv->base + RTCA3_RADJ);
> +	ret = readb_poll_timeout_atomic(priv->base + RTCA3_RADJ, tmp, (tmp == radj),
> +					10, RTCA3_DEFAULT_TIMEOUT_US);
> +unlock:
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	return ret;
> +}
> +
> +static const struct rtc_class_ops rtca3_ops = {
> +	.read_time = rtca3_read_time,
> +	.set_time = rtca3_set_time,
> +	.read_alarm = rtca3_read_alarm,
> +	.set_alarm = rtca3_set_alarm,
> +	.alarm_irq_enable = rtca3_alarm_irq_enable,
> +	.set_offset = rtca3_set_offset,
> +	.read_offset = rtca3_read_offset,
> +};
> +
> +static int rtca3_initial_setup(struct rtca3_priv *priv) {
> +	unsigned long osc32k_rate;
> +	u8 pes, tmp, mask;
> +	u32 sleep_us;
> +	int ret;
> +
> +	osc32k_rate = clk_get_rate(priv->clk);
> +	if (!osc32k_rate)
> +		return -EINVAL;
> +
> +	sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6;
> +
> +	priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10));
> +	priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL,
> +(osc32k_rate * 60));
> +
> +	/*
> +	 * According to HW manual (section 22.4.2. Clock and count mode setting procedure)
> +	 * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled.
> +	 */
> +	usleep_range(sleep_us, sleep_us + 10);
> +
> +	/* Disable alarm and carry interrupts. */
> +	mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE;
> +	rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, !(tmp & mask),
> +				 10, RTCA3_DEFAULT_TIMEOUT_US);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Stop the RTC and set to 12 hours mode and calendar count mode.
> +	 * RCR2.START initial value is undefined so we need to stop here
> +	 * all the time.
> +	 */
> +	mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24 | RTCA3_RCR2_CNTMD;
> +	writeb(0, priv->base + RTCA3_RCR2);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
> +				 10, RTCA3_DEFAULT_TIMEOUT_US);
> +	if (ret)
> +		return ret;
> +
> +	/* Execute reset and wait for reset and calendar count mode to be applied. */
> +	mask = RTCA3_RCR2_RESET | RTCA3_RCR2_CNTMD;
> +	writeb(RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
> +				 10, RTCA3_RESET_TIMEOUT_US);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * According to HW manual (section 22.6.3. Notes on writing to and reading
> +	 * from registers) after reset we need to wait 6 clock cycles before
> +	 * writing to RTC registers.
> +	 */
> +	usleep_range(sleep_us, sleep_us + 10);
> +
> +	/* Set no adjustment. */
> +	writeb(0, priv->base + RTCA3_RADJ);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10,
> +				 RTCA3_DEFAULT_TIMEOUT_US);
> +
> +	/* Start the RTC and enable automatic time error adjustment. */
> +	mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE;
> +	writeb(RTCA3_RCR2_START | RTCA3_RCR2_AADJE, priv->base + RTCA3_RCR2);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask),
> +				 10, RTCA3_START_TIMEOUT_US);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * According to HW manual (section 22.6.4. Notes on writing to and reading
> +	 * from registers) we need to wait 1/128 seconds while the clock is operating
> +	 * (RCR2.START bit = 1) to be able to read the counters after a return from
> +	 * reset.
> +	 */
> +	usleep_range(8000, 9000);
> +
> +	/* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */
> +	pes = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC);
> +	rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, pes);
> +	return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == pes),
> +				  10, RTCA3_DEFAULT_TIMEOUT_US);
> +}
> +
> +static int rtca3_request_irqs(struct platform_device *pdev, struct
> +rtca3_priv *priv) {
> +	struct device *dev = &pdev->dev;
> +	int ret, irq;
> +
> +	irq = platform_get_irq_byname(pdev, "alarm");
> +	if (irq < 0)
> +		return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n");
> +
> +	ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n");
> +	priv->wakeup_irq = irq;
> +
> +	irq = platform_get_irq_byname(pdev, "period");
> +	if (irq < 0)
> +		return dev_err_probe(dev, irq, "Failed to get period IRQ!\n");
> +
> +	ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to request period IRQ!\n");
> +
> +	/*
> +	 * Driver doesn't implement carry handler. Just get the IRQ here
> +	 * for backward compatibility, in case carry support will be added later.
> +	 */
> +	irq = platform_get_irq_byname(pdev, "carry");
> +	if (irq < 0)
> +		return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n");
> +
> +	return 0;
> +}
> +
> +static int rtca3_probe(struct platform_device *pdev) {
> +	struct device *dev = &pdev->dev;
> +	struct rtca3_priv *priv;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(priv->base))
> +		return PTR_ERR(priv->base);
> +
> +	priv->clk = devm_clk_get_enabled(dev, "counter");
> +	if (IS_ERR(priv->clk))
> +		return PTR_ERR(priv->clk);
> +
> +	platform_set_drvdata(pdev, priv);
> +
> +	spin_lock_init(&priv->lock);
> +	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
> +	init_completion(&priv->set_alarm_completion);
> +
> +	ret = rtca3_initial_setup(priv);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to setup the RTC!\n");
> +
> +	ret = rtca3_request_irqs(pdev, priv);
> +	if (ret)
> +		return ret;
> +
> +	device_init_wakeup(&pdev->dev, 1);
> +
> +	priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
> +	if (IS_ERR(priv->rtc_dev))
> +		return PTR_ERR(priv->rtc_dev);
> +
> +	priv->rtc_dev->ops = &rtca3_ops;
> +	priv->rtc_dev->max_user_freq = 256;
> +	priv->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0);
> +	priv->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59);
> +
> +	return devm_rtc_register_device(priv->rtc_dev);
> +}
> +
> +static void rtca3_remove(struct platform_device *pdev) {
> +	struct rtca3_priv *priv = platform_get_drvdata(pdev);
> +	u8 tmp, mask = RTCA3_RCR1_AIE | RTCA3_RCR1_PIE;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	/* Disable alarm, periodic interrupt. */
> +	rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0);
> +	readb_poll_timeout_atomic(priv->base + RTCA3_RCR1, tmp, !(tmp & mask),
> +				  10, RTCA3_IRQSET_TIMEOUT_US);
> +
> +	spin_unlock_irqrestore(&priv->lock, flags); }
> +
> +static int __maybe_unused rtca3_suspend(struct device *dev) {
> +	struct rtca3_priv *priv = dev_get_drvdata(dev);
> +
> +	if (!device_may_wakeup(dev))
> +		return 0;
> +
> +	/* Alarm setup in progress. */
> +	if (atomic_read(&priv->alrm_sstep) != RTCA3_ALRM_SSTEP_DONE)
> +		return -EBUSY;
> +
> +	enable_irq_wake(priv->wakeup_irq);
> +
> +	return 0;
> +}
> +
> +static int rtca3_clean_alarm(struct rtca3_priv *priv) {
> +	struct rtc_device *rtc_dev = priv->rtc_dev;
> +	time64_t alarm_time, now;
> +	struct rtc_wkalrm alarm;
> +	unsigned long flags;
> +	struct rtc_time tm;
> +	u8 pending;
> +	int ret;
> +
> +	ret = rtc_read_alarm(rtc_dev, &alarm);
> +	if (ret)
> +		return ret;
> +
> +	if (!alarm.enabled)
> +		return 0;
> +
> +	ret = rtc_read_time(rtc_dev, &tm);
> +	if (ret)
> +		return ret;
> +
> +	alarm_time = rtc_tm_to_time64(&alarm.time);
> +	now = rtc_tm_to_time64(&tm);
> +	if (alarm_time >= now)
> +		return 0;
> +
> +	/*
> +	 * Heuristically, it has been determined that when returning from deep
> +	 * sleep state the RTCA3_RSR.AF is zero even though the alarm expired.
> +	 * Call again the rtc_update_irq() if alarm helper detects this.
> +	 */
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +	pending = rtca3_alarm_handler_helper(priv);
> +	if (!pending)
> +		rtc_update_irq(priv->rtc_dev, 1, RTC_AF | RTC_IRQF);
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	return 0;
> +}
> +
> +static int __maybe_unused rtca3_resume(struct device *dev) {
> +	struct rtca3_priv *priv = dev_get_drvdata(dev);
> +
> +	if (!device_may_wakeup(dev))
> +		return 0;
> +
> +	disable_irq_wake(priv->wakeup_irq);
> +
> +	/*
> +	 * According to the HW manual (section 22.6.4 Notes on writing to
> +	 * and reading from registers) we need to wait 1/128 seconds while
> +	 * RCR2.START = 1 to be able to read the counters after a return from low
> +	 * power consumption state.
> +	 */
> +	mdelay(8);
> +
> +	/*
> +	 * The alarm cannot wake the system from deep sleep states. In case
> +	 * we return from deep sleep states and the alarm expired we need
> +	 * to disable it to avoid failures when setting another alarm.
> +	 */
> +	return rtca3_clean_alarm(priv);
> +}
> +
> +static SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume);
> +
> +static const struct of_device_id rtca3_of_match[] = {
> +	{ .compatible = "renesas,rzg3s-rtc", },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, rtca3_of_match);
> +
> +static struct platform_driver rtca3_platform_driver = {
> +	.driver = {
> +		.name = "rtc-rtca3",
> +		.pm = &rtca3_pm_ops,
> +		.of_match_table = rtca3_of_match,
> +	},
> +	.probe = rtca3_probe,
> +	.remove_new = rtca3_remove,
> +};
> +module_platform_driver(rtca3_platform_driver);
> +
> +MODULE_DESCRIPTION("Renesas RTCA-3 RTC driver"); MODULE_AUTHOR("Claudiu
> +Beznea <claudiu.beznea.uj@bp.renesas.com>");
> +MODULE_LICENSE("GPL");
> --
> 2.39.2
> 

RE: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[Biju Das]

Hi Claudiu,

Thanks for the patch.

> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On Behalf Of Claudiu
> Sent: Friday, June 14, 2024 8:19 AM
> Subject: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  .../bindings/rtc/renesas,rzg3s-rtc.yaml       | 60 +++++++++++++++++++
>  1 file changed, 60 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> new file mode 100644
> index 000000000000..0e17f8a36155
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/renesas,rzg3s-rtc.yaml#

Please make it generic renesas,rtca3-rtc.yaml. Future SoCs may use this IP.
So use IP name instead.

Cheers,
Biju

> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Real Time Clock for Renesas RZ/G3S SoC
> +
> +maintainers:
> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> +
> +properties:
> +  compatible:
> +    const: renesas,rzg3s-rtc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 3
> +
> +  interrupt-names:
> +    items:
> +      - const: alarm
> +      - const: period
> +      - const: carry
> +
> +  clocks:
> +    maxItems: 1
> +    description: RTC counter clock
> +
> +  clock-names:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    rtc: rtc@1004ec00 {
> +        compatible = "renesas,rzg3s-rtc";
> +        reg = <0x1004ec00 0x400>;
> +        interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "alarm", "period", "carry";
> +        clocks = <&vbattclk>;
> +        clock-names = "counter";
> +        status = "disabled";
> +    };
> --
> 2.39.2
> 

Re: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[claudiu beznea]

Hi, Biju,

On 14.06.2024 10:53, Biju Das wrote:
> Hi Claudiu,
> 
> Thanks for the patch.
> 
>> -----Original Message-----
>> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org> On Behalf Of Claudiu
>> Sent: Friday, June 14, 2024 8:19 AM
>> Subject: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC
>>
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  .../bindings/rtc/renesas,rzg3s-rtc.yaml       | 60 +++++++++++++++++++
>>  1 file changed, 60 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
>> b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
>> new file mode 100644
>> index 000000000000..0e17f8a36155
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
>> @@ -0,0 +1,60 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/rtc/renesas,rzg3s-rtc.yaml#
> 
> Please make it generic renesas,rtca3-rtc.yaml. Future SoCs may use this IP.
> So use IP name instead.

From what I know the file name should correspond with the compatible that
file was introduced with, and this one shouldn't be generic but SoC specific.

Thank you,
Claudiu Beznea

> 
> Cheers,
> Biju
> 
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Real Time Clock for Renesas RZ/G3S SoC
>> +
>> +maintainers:
>> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> +
>> +properties:
>> +  compatible:
>> +    const: renesas,rzg3s-rtc
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts:
>> +    maxItems: 3
>> +
>> +  interrupt-names:
>> +    items:
>> +      - const: alarm
>> +      - const: period
>> +      - const: carry
>> +
>> +  clocks:
>> +    maxItems: 1
>> +    description: RTC counter clock
>> +
>> +  clock-names:
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - interrupt-names
>> +  - clocks
>> +  - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +    rtc: rtc@1004ec00 {
>> +        compatible = "renesas,rzg3s-rtc";
>> +        reg = <0x1004ec00 0x400>;
>> +        interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
>> +        interrupt-names = "alarm", "period", "carry";
>> +        clocks = <&vbattclk>;
>> +        clock-names = "counter";
>> +        status = "disabled";
>> +    };
>> --
>> 2.39.2
>>
> 

RE: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[Biju Das]

> -----Original Message-----
> From: claudiu beznea <claudiu.beznea@tuxon.dev>
> Sent: Friday, June 14, 2024 9:17 AM
> To: Biju Das <biju.das.jz@bp.renesas.com>; geert+renesas@glider.be; mturquette@baylibre.com;
> sboyd@kernel.org; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; lee@kernel.org;
> alexandre.belloni@bootlin.com; magnus.damm@gmail.com
> Cc: linux-renesas-soc@vger.kernel.org; linux-clk@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-rtc@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> Subject: Re: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC
> 
> Hi, Biju,
> 
> On 14.06.2024 10:53, Biju Das wrote:
> > Hi Claudiu,
> >
> > Thanks for the patch.
> >
> >> -----Original Message-----
> >> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org>
> >> On Behalf Of Claudiu
> >> Sent: Friday, June 14, 2024 8:19 AM
> >> Subject: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document
> >> the Renesas RZ/G3S RTC
> >>
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> ---
> >>  .../bindings/rtc/renesas,rzg3s-rtc.yaml       | 60 +++++++++++++++++++
> >>  1 file changed, 60 insertions(+)
> >>  create mode 100644
> >> Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> >>
> >> diff --git
> >> a/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> >> b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> >> new file mode 100644
> >> index 000000000000..0e17f8a36155
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> >> @@ -0,0 +1,60 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/rtc/renesas,rzg3s-rtc.yaml#
> >
> > Please make it generic renesas,rtca3-rtc.yaml. Future SoCs may use this IP.
> > So use IP name instead.
> 
> From what I know the file name should correspond with the compatible that file was introduced with,
> and this one shouldn't be generic but SoC specific.

I maybe wrong, I was under the impression, we should use "vendor,ipname" for the filename
and compatible should use vendor,ipname as generic compatible.
If there are differences between SoCs, then use SoC specific compatible.

Currently there is one device, so not sure??

Cheers,
Biju



> 
> Thank you,
> Claudiu Beznea
> 
> >
> > Cheers,
> > Biju
> >
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: Real Time Clock for Renesas RZ/G3S SoC
> >> +
> >> +maintainers:
> >> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> +
> >> +properties:
> >> +  compatible:
> >> +    const: renesas,rzg3s-rtc
> >> +
> >> +  reg:
> >> +    maxItems: 1
> >> +
> >> +  interrupts:
> >> +    maxItems: 3
> >> +
> >> +  interrupt-names:
> >> +    items:
> >> +      - const: alarm
> >> +      - const: period
> >> +      - const: carry
> >> +
> >> +  clocks:
> >> +    maxItems: 1
> >> +    description: RTC counter clock
> >> +
> >> +  clock-names:
> >> +    maxItems: 1
> >> +
> >> +required:
> >> +  - compatible
> >> +  - reg
> >> +  - interrupts
> >> +  - interrupt-names
> >> +  - clocks
> >> +  - clock-names
> >> +
> >> +additionalProperties: false
> >> +
> >> +examples:
> >> +  - |
> >> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> >> +    #include <dt-bindings/interrupt-controller/irq.h>
> >> +
> >> +    rtc: rtc@1004ec00 {
> >> +        compatible = "renesas,rzg3s-rtc";
> >> +        reg = <0x1004ec00 0x400>;
> >> +        interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> >> +                     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> >> +                     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
> >> +        interrupt-names = "alarm", "period", "carry";
> >> +        clocks = <&vbattclk>;
> >> +        clock-names = "counter";
> >> +        status = "disabled";
> >> +    };
> >> --
> >> 2.39.2
> >>
> >

Re: [PATCH 06/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC

[Alexandre Belloni]

Hello Claudiu,

On 14/06/2024 10:19:26+0300, Claudiu wrote:
> +static int rtca3_initial_setup(struct rtca3_priv *priv)
> +{
> +	unsigned long osc32k_rate;
> +	u8 pes, tmp, mask;
> +	u32 sleep_us;
> +	int ret;
> +
> +	osc32k_rate = clk_get_rate(priv->clk);
> +	if (!osc32k_rate)
> +		return -EINVAL;
> +
> +	sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6;
> +
> +	priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10));
> +	priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60));
> +
> +	/*
> +	 * According to HW manual (section 22.4.2. Clock and count mode setting procedure)
> +	 * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled.
> +	 */
> +	usleep_range(sleep_us, sleep_us + 10);
> +
> +	/* Disable alarm and carry interrupts. */
> +	mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE;
> +	rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, !(tmp & mask),
> +				 10, RTCA3_DEFAULT_TIMEOUT_US);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Stop the RTC and set to 12 hours mode and calendar count mode.
> +	 * RCR2.START initial value is undefined so we need to stop here
> +	 * all the time.
> +	 */

Certainly not, if you stop the RTC on probe, you lose the time
information, this must only be done when the RTC has never been
initialised. The whole goal of the RTC is the keep time across reboots,
its lifecycle is longer than the system.

Also, why do you insist on 12H-mode? The proper thing to do is to support
12H-mode on read but always use 24H-mode when setting the time.

> +	mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24 | RTCA3_RCR2_CNTMD;
> +	writeb(0, priv->base + RTCA3_RCR2);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
> +				 10, RTCA3_DEFAULT_TIMEOUT_US);
> +	if (ret)
> +		return ret;
> +
> +	/* Execute reset and wait for reset and calendar count mode to be applied. */
> +	mask = RTCA3_RCR2_RESET | RTCA3_RCR2_CNTMD;
> +	writeb(RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
> +				 10, RTCA3_RESET_TIMEOUT_US);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * According to HW manual (section 22.6.3. Notes on writing to and reading
> +	 * from registers) after reset we need to wait 6 clock cycles before
> +	 * writing to RTC registers.
> +	 */
> +	usleep_range(sleep_us, sleep_us + 10);
> +
> +	/* Set no adjustment. */
> +	writeb(0, priv->base + RTCA3_RADJ);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10,
> +				 RTCA3_DEFAULT_TIMEOUT_US);
> +
> +	/* Start the RTC and enable automatic time error adjustment. */
> +	mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE;
> +	writeb(RTCA3_RCR2_START | RTCA3_RCR2_AADJE, priv->base + RTCA3_RCR2);
> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask),
> +				 10, RTCA3_START_TIMEOUT_US);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * According to HW manual (section 22.6.4. Notes on writing to and reading
> +	 * from registers) we need to wait 1/128 seconds while the clock is operating
> +	 * (RCR2.START bit = 1) to be able to read the counters after a return from
> +	 * reset.
> +	 */
> +	usleep_range(8000, 9000);
> +
> +	/* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */
> +	pes = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC);
> +	rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, pes);
> +	return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == pes),
> +				  10, RTCA3_DEFAULT_TIMEOUT_US);
> +}
> +
> +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv)
> +{
> +	struct device *dev = &pdev->dev;
> +	int ret, irq;
> +
> +	irq = platform_get_irq_byname(pdev, "alarm");
> +	if (irq < 0)
> +		return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n");
> +
> +	ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n");
> +	priv->wakeup_irq = irq;
> +
> +	irq = platform_get_irq_byname(pdev, "period");
> +	if (irq < 0)
> +		return dev_err_probe(dev, irq, "Failed to get period IRQ!\n");
> +
> +	ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to request period IRQ!\n");
> +
> +	/*
> +	 * Driver doesn't implement carry handler. Just get the IRQ here
> +	 * for backward compatibility, in case carry support will be added later.
> +	 */
> +	irq = platform_get_irq_byname(pdev, "carry");
> +	if (irq < 0)
> +		return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n");
> +
> +	return 0;
> +}
> +
> +static int rtca3_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct rtca3_priv *priv;
> +	int ret;
> +
> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> +	if (!priv)
> +		return -ENOMEM;
> +
> +	priv->base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(priv->base))
> +		return PTR_ERR(priv->base);
> +
> +	priv->clk = devm_clk_get_enabled(dev, "counter");
> +	if (IS_ERR(priv->clk))
> +		return PTR_ERR(priv->clk);
> +
> +	platform_set_drvdata(pdev, priv);
> +
> +	spin_lock_init(&priv->lock);
> +	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
> +	init_completion(&priv->set_alarm_completion);
> +
> +	ret = rtca3_initial_setup(priv);
> +	if (ret)
> +		return dev_err_probe(dev, ret, "Failed to setup the RTC!\n");
> +
> +	ret = rtca3_request_irqs(pdev, priv);
> +	if (ret)
> +		return ret;
> +
> +	device_init_wakeup(&pdev->dev, 1);
> +
> +	priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
> +	if (IS_ERR(priv->rtc_dev))
> +		return PTR_ERR(priv->rtc_dev);
> +
> +	priv->rtc_dev->ops = &rtca3_ops;
> +	priv->rtc_dev->max_user_freq = 256;
> +	priv->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0);
> +	priv->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59);

This very much looks like the range should be 2000 to 2099, why do you
want to shift it?


-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH 06/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC

[claudiu beznea]

Hi, Alexandre,

On 14.06.2024 12:21, Alexandre Belloni wrote:
> Hello Claudiu,
> 
> On 14/06/2024 10:19:26+0300, Claudiu wrote:
>> +static int rtca3_initial_setup(struct rtca3_priv *priv)
>> +{
>> +	unsigned long osc32k_rate;
>> +	u8 pes, tmp, mask;
>> +	u32 sleep_us;
>> +	int ret;
>> +
>> +	osc32k_rate = clk_get_rate(priv->clk);
>> +	if (!osc32k_rate)
>> +		return -EINVAL;
>> +
>> +	sleep_us = DIV_ROUND_UP_ULL(1000000ULL, osc32k_rate) * 6;
>> +
>> +	priv->ppb.ten_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 10));
>> +	priv->ppb.sixty_sec = DIV_ROUND_CLOSEST_ULL(1000000000ULL, (osc32k_rate * 60));
>> +
>> +	/*
>> +	 * According to HW manual (section 22.4.2. Clock and count mode setting procedure)
>> +	 * we need to wait at least 6 cycles of the 32KHz clock after clock was enabled.
>> +	 */
>> +	usleep_range(sleep_us, sleep_us + 10);
>> +
>> +	/* Disable alarm and carry interrupts. */
>> +	mask = RTCA3_RCR1_AIE | RTCA3_RCR1_CIE;
>> +	rtca3_byte_update_bits(priv, RTCA3_RCR1, mask, 0);
>> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, !(tmp & mask),
>> +				 10, RTCA3_DEFAULT_TIMEOUT_US);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/*
>> +	 * Stop the RTC and set to 12 hours mode and calendar count mode.
>> +	 * RCR2.START initial value is undefined so we need to stop here
>> +	 * all the time.
>> +	 */
> 
> Certainly not, if you stop the RTC on probe, you lose the time
> information, this must only be done when the RTC has never been
> initialised. The whole goal of the RTC is the keep time across reboots,
> its lifecycle is longer than the system.

This was also my first thought when I read the HW manual.

It has been done like this to follow the HW manual. According to HW manual
[1], chapter 22.3.19 RTC Control Register 2 (RCR2), initial value of START
bit is undefined.

If it's 1 while probing but it has never been initialized, we can falsely
detect that RTC is started and skip the rest of the initialization steps.
W/o initialization configuration, the RTC will not be able to work.

Even with this implementation we don't loose the time b/w reboots. Here is
the output on my board [2]. The steps I did were the following:
1/ remove the power to the board (I don't have a battery for RTC installed
   at the moment)
2/ boot the board and issue hwclock -w
3/ reboot
4/ check the systime and rtc time
5/ poweroff
6/ poweron
7/ boot and check systime and RTC time

As you can see the time is not lost but continue to increment. I presume
the hardware takes into account that time needs to increment when initial
configuration is executed.

[1]
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250
[2] https://p.fr33tux.org/585cd6

> 
> Also, why do you insist on 12H-mode? The proper thing to do is to support
> 12H-mode on read but always use 24H-mode when setting the time.

OK, I wasn't aware of this. I think I followed this approach as it looked
to me the number of operation to update the hardware registers was lower
for 12h mode.

I'll adjust as proposed.

> 
>> +	mask = RTCA3_RCR2_START | RTCA3_RCR2_HR24 | RTCA3_RCR2_CNTMD;
>> +	writeb(0, priv->base + RTCA3_RCR2);
>> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
>> +				 10, RTCA3_DEFAULT_TIMEOUT_US);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* Execute reset and wait for reset and calendar count mode to be applied. */
>> +	mask = RTCA3_RCR2_RESET | RTCA3_RCR2_CNTMD;
>> +	writeb(RTCA3_RCR2_RESET, priv->base + RTCA3_RCR2);
>> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, !(tmp & mask),
>> +				 10, RTCA3_RESET_TIMEOUT_US);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/*
>> +	 * According to HW manual (section 22.6.3. Notes on writing to and reading
>> +	 * from registers) after reset we need to wait 6 clock cycles before
>> +	 * writing to RTC registers.
>> +	 */
>> +	usleep_range(sleep_us, sleep_us + 10);
>> +
>> +	/* Set no adjustment. */
>> +	writeb(0, priv->base + RTCA3_RADJ);
>> +	ret = readb_poll_timeout(priv->base + RTCA3_RADJ, tmp, !tmp, 10,
>> +				 RTCA3_DEFAULT_TIMEOUT_US);
>> +
>> +	/* Start the RTC and enable automatic time error adjustment. */
>> +	mask = RTCA3_RCR2_START | RTCA3_RCR2_AADJE;
>> +	writeb(RTCA3_RCR2_START | RTCA3_RCR2_AADJE, priv->base + RTCA3_RCR2);
>> +	ret = readb_poll_timeout(priv->base + RTCA3_RCR2, tmp, ((tmp & mask) == mask),
>> +				 10, RTCA3_START_TIMEOUT_US);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/*
>> +	 * According to HW manual (section 22.6.4. Notes on writing to and reading
>> +	 * from registers) we need to wait 1/128 seconds while the clock is operating
>> +	 * (RCR2.START bit = 1) to be able to read the counters after a return from
>> +	 * reset.
>> +	 */
>> +	usleep_range(8000, 9000);
>> +
>> +	/* Set period interrupt to 1/64 seconds. It is necessary for alarm setup. */
>> +	pes = FIELD_PREP(RTCA3_RCR1_PES, RTCA3_RCR1_PES_1_64_SEC);
>> +	rtca3_byte_update_bits(priv, RTCA3_RCR1, RTCA3_RCR1_PES, pes);
>> +	return readb_poll_timeout(priv->base + RTCA3_RCR1, tmp, ((tmp & RTCA3_RCR1_PES) == pes),
>> +				  10, RTCA3_DEFAULT_TIMEOUT_US);
>> +}
>> +
>> +static int rtca3_request_irqs(struct platform_device *pdev, struct rtca3_priv *priv)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	int ret, irq;
>> +
>> +	irq = platform_get_irq_byname(pdev, "alarm");
>> +	if (irq < 0)
>> +		return dev_err_probe(dev, irq, "Failed to get alarm IRQ!\n");
>> +
>> +	ret = devm_request_irq(dev, irq, rtca3_alarm_handler, 0, "rtca3-alarm", priv);
>> +	if (ret)
>> +		return dev_err_probe(dev, ret, "Failed to request alarm IRQ!\n");
>> +	priv->wakeup_irq = irq;
>> +
>> +	irq = platform_get_irq_byname(pdev, "period");
>> +	if (irq < 0)
>> +		return dev_err_probe(dev, irq, "Failed to get period IRQ!\n");
>> +
>> +	ret = devm_request_irq(dev, irq, rtca3_periodic_handler, 0, "rtca3-period", priv);
>> +	if (ret)
>> +		return dev_err_probe(dev, ret, "Failed to request period IRQ!\n");
>> +
>> +	/*
>> +	 * Driver doesn't implement carry handler. Just get the IRQ here
>> +	 * for backward compatibility, in case carry support will be added later.
>> +	 */
>> +	irq = platform_get_irq_byname(pdev, "carry");
>> +	if (irq < 0)
>> +		return dev_err_probe(dev, irq, "Failed to get carry IRQ!\n");
>> +
>> +	return 0;
>> +}
>> +
>> +static int rtca3_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	struct rtca3_priv *priv;
>> +	int ret;
>> +
>> +	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
>> +	if (!priv)
>> +		return -ENOMEM;
>> +
>> +	priv->base = devm_platform_ioremap_resource(pdev, 0);
>> +	if (IS_ERR(priv->base))
>> +		return PTR_ERR(priv->base);
>> +
>> +	priv->clk = devm_clk_get_enabled(dev, "counter");
>> +	if (IS_ERR(priv->clk))
>> +		return PTR_ERR(priv->clk);
>> +
>> +	platform_set_drvdata(pdev, priv);
>> +
>> +	spin_lock_init(&priv->lock);
>> +	atomic_set(&priv->alrm_sstep, RTCA3_ALRM_SSTEP_DONE);
>> +	init_completion(&priv->set_alarm_completion);
>> +
>> +	ret = rtca3_initial_setup(priv);
>> +	if (ret)
>> +		return dev_err_probe(dev, ret, "Failed to setup the RTC!\n");
>> +
>> +	ret = rtca3_request_irqs(pdev, priv);
>> +	if (ret)
>> +		return ret;
>> +
>> +	device_init_wakeup(&pdev->dev, 1);
>> +
>> +	priv->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
>> +	if (IS_ERR(priv->rtc_dev))
>> +		return PTR_ERR(priv->rtc_dev);
>> +
>> +	priv->rtc_dev->ops = &rtca3_ops;
>> +	priv->rtc_dev->max_user_freq = 256;
>> +	priv->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0);
>> +	priv->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59);
> 
> This very much looks like the range should be 2000 to 2099, why do you
> want to shift it?

2000-2099 was my first option for this but then I saw one of your old
commits on this topic and, since I'm not very familiar with RTC,
I took it as example. I'll adjust as you proposed.

commit beee05dfbead
Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
Date:   Wed Mar 20 12:30:10 2019 +0100

    rtc: sh: set range

    The SH RTC is a BCD RTC with some version having 4 digits for the year.

    The range for the RTCs with only 2 digits for the year was unfortunately
    shifted to handle 1999 to 2098.

    Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
    Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>


Thank you for your review,
Claudiu Beznea

> 
> 

Re: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[Conor Dooley]

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On Fri, Jun 14, 2024 at 08:22:57AM +0000, Biju Das wrote:

> > >> +$id: http://devicetree.org/schemas/rtc/renesas,rzg3s-rtc.yaml#
> > >
> > > Please make it generic renesas,rtca3-rtc.yaml. Future SoCs may use this IP.
> > > So use IP name instead.
> > 
> > From what I know the file name should correspond with the compatible that file was introduced with,
> > and this one shouldn't be generic but SoC specific.
> 
> I maybe wrong, I was under the impression, we should use "vendor,ipname" for the filename
> and compatible should use vendor,ipname as generic compatible.
> If there are differences between SoCs, then use SoC specific compatible.
> 
> Currently there is one device, so not sure??

The usual policy for new files is "filename matching a compatible".

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Re: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver

[Conor Dooley]

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On Fri, Jun 14, 2024 at 10:19:22AM +0300, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feeds
> the RTC and the tamper detector. Add documentation for the VBATTB clock
> driver.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  .../clock/renesas,rzg3s-vbattb-clk.yaml       | 90 +++++++++++++++++++
>  1 file changed, 90 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
> new file mode 100644
> index 000000000000..ef52a0c0f874
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,rzg3s-vbattb-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas VBATTB clock
> +
> +maintainers:
> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> +
> +description:
> +  Renesas VBATTB module is an always on powered module (backed by battery) which
> +  generates a clock (VBATTCLK). This clocks feeds the RTC and the tamper detector
> +  modules.
> +
> +properties:
> +  compatible:
> +    const: renesas,rzg3s-vbattb-clk
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: VBATTB module clock
> +      - description: VBATTB input xtal
> +
> +  clock-names:
> +    items:
> +      - const: bclk
> +      - const: vbattb_xtal
> +
> +  '#clock-cells':
> +    const: 0
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  renesas,vbattb-load-nanofarads:
> +    description: load capacitance of the on board xtal
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 4000, 7000, 9000, 12500 ]
> +
> +  renesas,vbattb-osc-bypass:
> +    description: set when external clock is connected to RTXOUT pin
> +    type: boolean

When you say "external clock", is that an input or an output?

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Re: [PATCH 03/12] dt-bindings: mfd: renesas,rzg3s-vbattb: Document VBATTB

[Conor Dooley]

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On Fri, Jun 14, 2024 at 10:19:23AM +0300, Claudiu wrote:
> +patternProperties:
> +  "^clock-controller@[0-9a-f]+$":
> +    $ref: /schemas/clock/renesas,rzg3s-vbattb-clk.yaml#
> +    description: VBATTCLK clock

Being a bit of a pedant here, but isn't the address known? You leaving
room for future devices with it at a different offset?

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Re: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[Conor Dooley]

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On Fri, Jun 14, 2024 at 10:19:25AM +0300, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
>  .../bindings/rtc/renesas,rzg3s-rtc.yaml       | 60 +++++++++++++++++++
>  1 file changed, 60 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> 
> diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> new file mode 100644
> index 000000000000..0e17f8a36155
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/rtc/renesas,rzg3s-rtc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Real Time Clock for Renesas RZ/G3S SoC
> +
> +maintainers:
> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> +

Missing a ref to adc.yaml, or can this rtc not serve as a wakeup-source
or use any of the common properties?

Cheers,
Conor.

> +properties:
> +  compatible:
> +    const: renesas,rzg3s-rtc
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 3
> +
> +  interrupt-names:
> +    items:
> +      - const: alarm
> +      - const: period
> +      - const: carry
> +
> +  clocks:
> +    maxItems: 1
> +    description: RTC counter clock
> +
> +  clock-names:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    rtc: rtc@1004ec00 {
> +        compatible = "renesas,rzg3s-rtc";
> +        reg = <0x1004ec00 0x400>;
> +        interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "alarm", "period", "carry";
> +        clocks = <&vbattclk>;
> +        clock-names = "counter";
> +        status = "disabled";
> +    };
> -- 
> 2.39.2
> 

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Re: [PATCH 04/12] clk: renesas: clk-vbattb: Add VBATTB clock driver

[kernel test robot]

Hi Claudiu,

kernel test robot noticed the following build warnings:

[auto build test WARNING on geert-renesas-drivers/renesas-clk]
[also build test WARNING on geert-renesas-devel/next linus/master v6.10-rc3 next-20240613]
[cannot apply to abelloni/rtc-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Claudiu/clk-renesas-r9a08g045-Add-clock-reset-and-power-domain-support-for-the-VBATTB-IP/20240614-152418
base:   https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link:    https://lore.kernel.org/r/20240614071932.1014067-5-claudiu.beznea.uj%40bp.renesas.com
patch subject: [PATCH 04/12] clk: renesas: clk-vbattb: Add VBATTB clock driver
config: arm64-randconfig-r131-20240615 (https://download.01.org/0day-ci/archive/20240616/202406160533.s4RRLDes-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240616/202406160533.s4RRLDes-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406160533.s4RRLDes-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/clk/renesas/clk-vbattb.c:132:35: sparse: sparse: incorrect type in argument 2 (different base types) @@     expected unsigned long [usertype] size @@     got restricted gfp_t @@
   drivers/clk/renesas/clk-vbattb.c:132:35: sparse:     expected unsigned long [usertype] size
   drivers/clk/renesas/clk-vbattb.c:132:35: sparse:     got restricted gfp_t
>> drivers/clk/renesas/clk-vbattb.c:132:47: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected restricted gfp_t [usertype] gfp @@     got unsigned long @@
   drivers/clk/renesas/clk-vbattb.c:132:47: sparse:     expected restricted gfp_t [usertype] gfp
   drivers/clk/renesas/clk-vbattb.c:132:47: sparse:     got unsigned long
   drivers/clk/renesas/clk-vbattb.c: note: in included file (through include/linux/mmzone.h, include/linux/gfp.h, include/linux/xarray.h, ...):
   include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false
   include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false

vim +132 drivers/clk/renesas/clk-vbattb.c

   119	
   120	static int vbattb_clk_probe(struct platform_device *pdev)
   121	{
   122		struct clk_parent_data parent_data = { .fw_name = "vbattb_xtal" };
   123		struct device_node *np = pdev->dev.of_node;
   124		struct device *dev = &pdev->dev;
   125		struct clk_init_data init = {};
   126		struct vbattb_clk *vbclk;
   127		u32 load_capacitance;
   128		struct clk_hw *hw;
   129		bool bypass;
   130		int ret;
   131	
 > 132		vbclk = devm_kzalloc(dev, GFP_KERNEL, sizeof(*vbclk));
   133		if (!vbclk)
   134			return -ENOMEM;
   135	
   136		vbclk->regmap = syscon_node_to_regmap(np->parent);
   137		if (IS_ERR(vbclk->regmap))
   138			return PTR_ERR(vbclk->regmap);
   139	
   140		bypass = of_property_read_bool(np, "renesas,vbattb-osc-bypass");
   141		ret = of_property_read_u32(np, "renesas,vbattb-load-nanofarads", &load_capacitance);
   142		if (ret)
   143			return ret;
   144	
   145		ret = vbattb_clk_validate_load_capacitance(vbclk, load_capacitance);
   146		if (ret)
   147			return ret;
   148	
   149		ret = devm_pm_runtime_enable(dev);
   150		if (ret)
   151			return ret;
   152	
   153		ret = pm_runtime_resume_and_get(dev);
   154		if (ret)
   155			return ret;
   156	
   157		regmap_update_bits(vbclk->regmap, VBATTB_BKSCCR, VBATTB_BKSCCR_SOSEL,
   158				   bypass ? VBATTB_BKSCCR_SOSEL : 0);
   159	
   160		init.name = "vbattclk";
   161		init.ops = &vbattb_clk_ops;
   162		init.parent_data = &parent_data;
   163		init.num_parents = 1;
   164		init.flags = 0;
   165	
   166		vbclk->hw.init = &init;
   167		hw = &vbclk->hw;
   168	
   169		spin_lock_init(&vbclk->lock);
   170	
   171		ret = devm_clk_hw_register(dev, hw);
   172		if (ret)
   173			goto rpm_put;
   174	
   175		ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
   176		if (ret)
   177			goto rpm_put;
   178	
   179		return 0;
   180	
   181	rpm_put:
   182		pm_runtime_put(dev);
   183		return ret;
   184	}
   185	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 04/12] clk: renesas: clk-vbattb: Add VBATTB clock driver

[kernel test robot]

Hi Claudiu,

kernel test robot noticed the following build warnings:

[auto build test WARNING on geert-renesas-drivers/renesas-clk]
[also build test WARNING on geert-renesas-devel/next linus/master v6.10-rc3 next-20240613]
[cannot apply to abelloni/rtc-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Claudiu/clk-renesas-r9a08g045-Add-clock-reset-and-power-domain-support-for-the-VBATTB-IP/20240614-152418
base:   https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link:    https://lore.kernel.org/r/20240614071932.1014067-5-claudiu.beznea.uj%40bp.renesas.com
patch subject: [PATCH 04/12] clk: renesas: clk-vbattb: Add VBATTB clock driver
config: mips-randconfig-r122-20240616 (https://download.01.org/0day-ci/archive/20240616/202406160847.Ns62KOVc-lkp@intel.com/config)
compiler: mips-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240616/202406160847.Ns62KOVc-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202406160847.Ns62KOVc-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/clk/renesas/clk-vbattb.c:132:35: sparse: sparse: incorrect type in argument 2 (different base types) @@     expected unsigned int [usertype] size @@     got restricted gfp_t @@
   drivers/clk/renesas/clk-vbattb.c:132:35: sparse:     expected unsigned int [usertype] size
   drivers/clk/renesas/clk-vbattb.c:132:35: sparse:     got restricted gfp_t
>> drivers/clk/renesas/clk-vbattb.c:132:47: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected restricted gfp_t [usertype] gfp @@     got unsigned int @@
   drivers/clk/renesas/clk-vbattb.c:132:47: sparse:     expected restricted gfp_t [usertype] gfp
   drivers/clk/renesas/clk-vbattb.c:132:47: sparse:     got unsigned int
   drivers/clk/renesas/clk-vbattb.c: note: in included file (through include/linux/mmzone.h, include/linux/gfp.h, include/linux/xarray.h, ...):
   include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false
   include/linux/page-flags.h:240:46: sparse: sparse: self-comparison always evaluates to false

vim +132 drivers/clk/renesas/clk-vbattb.c

   119	
   120	static int vbattb_clk_probe(struct platform_device *pdev)
   121	{
   122		struct clk_parent_data parent_data = { .fw_name = "vbattb_xtal" };
   123		struct device_node *np = pdev->dev.of_node;
   124		struct device *dev = &pdev->dev;
   125		struct clk_init_data init = {};
   126		struct vbattb_clk *vbclk;
   127		u32 load_capacitance;
   128		struct clk_hw *hw;
   129		bool bypass;
   130		int ret;
   131	
 > 132		vbclk = devm_kzalloc(dev, GFP_KERNEL, sizeof(*vbclk));
   133		if (!vbclk)
   134			return -ENOMEM;
   135	
   136		vbclk->regmap = syscon_node_to_regmap(np->parent);
   137		if (IS_ERR(vbclk->regmap))
   138			return PTR_ERR(vbclk->regmap);
   139	
   140		bypass = of_property_read_bool(np, "renesas,vbattb-osc-bypass");
   141		ret = of_property_read_u32(np, "renesas,vbattb-load-nanofarads", &load_capacitance);
   142		if (ret)
   143			return ret;
   144	
   145		ret = vbattb_clk_validate_load_capacitance(vbclk, load_capacitance);
   146		if (ret)
   147			return ret;
   148	
   149		ret = devm_pm_runtime_enable(dev);
   150		if (ret)
   151			return ret;
   152	
   153		ret = pm_runtime_resume_and_get(dev);
   154		if (ret)
   155			return ret;
   156	
   157		regmap_update_bits(vbclk->regmap, VBATTB_BKSCCR, VBATTB_BKSCCR_SOSEL,
   158				   bypass ? VBATTB_BKSCCR_SOSEL : 0);
   159	
   160		init.name = "vbattclk";
   161		init.ops = &vbattb_clk_ops;
   162		init.parent_data = &parent_data;
   163		init.num_parents = 1;
   164		init.flags = 0;
   165	
   166		vbclk->hw.init = &init;
   167		hw = &vbclk->hw;
   168	
   169		spin_lock_init(&vbclk->lock);
   170	
   171		ret = devm_clk_hw_register(dev, hw);
   172		if (ret)
   173			goto rpm_put;
   174	
   175		ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
   176		if (ret)
   177			goto rpm_put;
   178	
   179		return 0;
   180	
   181	rpm_put:
   182		pm_runtime_put(dev);
   183		return ret;
   184	}
   185	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 03/12] dt-bindings: mfd: renesas,rzg3s-vbattb: Document VBATTB

[Krzysztof Kozlowski]

On 14/06/2024 09:19, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

> +
> +maintainers:
> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: renesas,rzg3s-vbattb
> +      - const: syscon
> +      - const: simple-mfd

No, mfd does no look good. That's not a simple device anymore and you
claim here child does not need vbat bclk, power domains and resets? That
would be a big surprise, although technically possible.

Please clarify: which of parent resources are needed for children?

...

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    vbattb: vbattb@1005c000 {
> +        compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
> +        reg = <0x1005c000 0x1000>;
> +        ranges = <0 0 0x1005c000 0 0x1000>;
> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "tampdi";
> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
> +        clock-names = "bclk";
> +        power-domains = <&cpg>;
> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        status = "disabled";

Drop

> +
> +        vbattclk: clock-controller@1c {
> +            compatible = "renesas,rzg3s-vbattb-clk";
> +            reg = <0 0x1c 0 0x10>;
> +            clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
> +            clock-names = "bclk", "vbattb_xtal";
> +            #clock-cells = <0>;
> +            power-domains = <&cpg>;
> +            status = "disabled";

Drop

> +        };
> +    };
> +
> +...

Best regards,
Krzysztof

Re: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver

[Krzysztof Kozlowski]

On 14/06/2024 09:19, Claudiu wrote:
> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    vbattb: vbattb@1005c000 {
> +        compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
> +        reg = <0x1005c000 0x1000>;
> +        ranges = <0 0 0x1005c000 0 0x1000>;
> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "tampdi";
> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
> +        clock-names = "bclk";
> +        power-domains = <&cpg>;
> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +        status = "disabled";

Drop.

And keep only one complete example, instead of two. See other complex
devices as example.


Best regards,
Krzysztof

Re: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[Krzysztof Kozlowski]

On 14/06/2024 09:19, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.

> +
> +  clocks:
> +    maxItems: 1
> +    description: RTC counter clock

Just items: with description instead.

> +
> +  clock-names:
> +    maxItems: 1

Nope, it must be specifc. Or just drop. This applies to all your patches.

> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    rtc: rtc@1004ec00 {

Drop label, not used.

> +        compatible = "renesas,rzg3s-rtc";
> +        reg = <0x1004ec00 0x400>;
> +        interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
> +        interrupt-names = "alarm", "period", "carry";
> +        clocks = <&vbattclk>;
> +        clock-names = "counter";
> +        status = "disabled";

Why do you paste it eevrywhere? It does no really make sense.

Best regards,
Krzysztof

Re: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver

[claudiu beznea]

On 15.06.2024 15:17, Conor Dooley wrote:
> On Fri, Jun 14, 2024 at 10:19:22AM +0300, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feeds
>> the RTC and the tamper detector. Add documentation for the VBATTB clock
>> driver.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  .../clock/renesas,rzg3s-vbattb-clk.yaml       | 90 +++++++++++++++++++
>>  1 file changed, 90 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
>> new file mode 100644
>> index 000000000000..ef52a0c0f874
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
>> @@ -0,0 +1,90 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/renesas,rzg3s-vbattb-clk.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Renesas VBATTB clock
>> +
>> +maintainers:
>> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> +
>> +description:
>> +  Renesas VBATTB module is an always on powered module (backed by battery) which
>> +  generates a clock (VBATTCLK). This clocks feeds the RTC and the tamper detector
>> +  modules.
>> +
>> +properties:
>> +  compatible:
>> +    const: renesas,rzg3s-vbattb-clk
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  clocks:
>> +    items:
>> +      - description: VBATTB module clock
>> +      - description: VBATTB input xtal
>> +
>> +  clock-names:
>> +    items:
>> +      - const: bclk
>> +      - const: vbattb_xtal
>> +
>> +  '#clock-cells':
>> +    const: 0
>> +
>> +  power-domains:
>> +    maxItems: 1
>> +
>> +  renesas,vbattb-load-nanofarads:
>> +    description: load capacitance of the on board xtal
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    enum: [ 4000, 7000, 9000, 12500 ]
>> +
>> +  renesas,vbattb-osc-bypass:
>> +    description: set when external clock is connected to RTXOUT pin
>> +    type: boolean
> 
> When you say "external clock", is that an input or an output?

I took that statement from the HW manual. As of the HW manual [1], table
42.2, that would be an input.

[1]
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250

Re: [PATCH 03/12] dt-bindings: mfd: renesas,rzg3s-vbattb: Document VBATTB

[claudiu beznea]

On 15.06.2024 15:19, Conor Dooley wrote:
> On Fri, Jun 14, 2024 at 10:19:23AM +0300, Claudiu wrote:
>> +patternProperties:
>> +  "^clock-controller@[0-9a-f]+$":
>> +    $ref: /schemas/clock/renesas,rzg3s-vbattb-clk.yaml#
>> +    description: VBATTCLK clock
> 
> Being a bit of a pedant here, but isn't the address known? 

It is.

> You leaving
> room for future devices with it at a different offset?

Ok, I'll keep it 1c instead.

Thank you for your review,
Claudiu Beznea

Re: [PATCH 03/12] dt-bindings: mfd: renesas,rzg3s-vbattb: Document VBATTB

[claudiu beznea]

On 16.06.2024 10:38, Krzysztof Kozlowski wrote:
> On 14/06/2024 09:19, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
>> +
>> +maintainers:
>> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - const: renesas,rzg3s-vbattb
>> +      - const: syscon
>> +      - const: simple-mfd
> 
> No, mfd does no look good. That's not a simple device anymore and you
> claim here child does not need vbat bclk, power domains and resets? That
> would be a big surprise, although technically possible.

I wasn't sure how this MFD will be received by the Renesas maintainers so I
kept it simple for this version.

In theory the VBAT clk, power domain and resets are specific to VBAT module
itself but, indeed, the child cannot work w/o these.

> 
> Please clarify: which of parent resources are needed for children?

VBAT clock, power domain are needed. Reset, too. In the current
implementation the reset is deasserted though parent by calling the
syscon_node_to_regmap(np->parent) in the clock driver.

> 
> ...
> 
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +    vbattb: vbattb@1005c000 {
>> +        compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
>> +        reg = <0x1005c000 0x1000>;
>> +        ranges = <0 0 0x1005c000 0 0x1000>;
>> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>> +        interrupt-names = "tampdi";
>> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
>> +        clock-names = "bclk";
>> +        power-domains = <&cpg>;
>> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +        status = "disabled";
> 
> Drop

Could you please clarify this? Would you want me to drop the full node
(same for clock-controller node)?

Can you point me an example that you are thinking about?

Thank you,
Claudiu Beznea

> 
>> +
>> +        vbattclk: clock-controller@1c {
>> +            compatible = "renesas,rzg3s-vbattb-clk";
>> +            reg = <0 0x1c 0 0x10>;
>> +            clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
>> +            clock-names = "bclk", "vbattb_xtal";
>> +            #clock-cells = <0>;
>> +            power-domains = <&cpg>;
>> +            status = "disabled";
> 
> Drop
> 
>> +        };
>> +    };
>> +
>> +...
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[claudiu beznea]

On 15.06.2024 15:20, Conor Dooley wrote:
> On Fri, Jun 14, 2024 at 10:19:25AM +0300, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>  .../bindings/rtc/renesas,rzg3s-rtc.yaml       | 60 +++++++++++++++++++
>>  1 file changed, 60 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
>> new file mode 100644
>> index 000000000000..0e17f8a36155
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
>> @@ -0,0 +1,60 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/rtc/renesas,rzg3s-rtc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Real Time Clock for Renesas RZ/G3S SoC
>> +
>> +maintainers:
>> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> +
> 
> Missing a ref to adc.yaml,

I guess you mean rtc.yaml?

I missed that rtc.yaml. I'll update it.

> or can this rtc not serve as a wakeup-source
> or use any of the common properties?

It can act as wakeup-source but not for all the supported power save modes.

> 
> Cheers,
> Conor.
> 
>> +properties:
>> +  compatible:
>> +    const: renesas,rzg3s-rtc
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts:
>> +    maxItems: 3
>> +
>> +  interrupt-names:
>> +    items:
>> +      - const: alarm
>> +      - const: period
>> +      - const: carry
>> +
>> +  clocks:
>> +    maxItems: 1
>> +    description: RTC counter clock
>> +
>> +  clock-names:
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - interrupt-names
>> +  - clocks
>> +  - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +    rtc: rtc@1004ec00 {
>> +        compatible = "renesas,rzg3s-rtc";
>> +        reg = <0x1004ec00 0x400>;
>> +        interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
>> +        interrupt-names = "alarm", "period", "carry";
>> +        clocks = <&vbattclk>;
>> +        clock-names = "counter";
>> +        status = "disabled";
>> +    };
>> -- 
>> 2.39.2
>>

Re: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[claudiu beznea]

On 16.06.2024 10:40, Krzysztof Kozlowski wrote:
> On 14/06/2024 09:19, Claudiu wrote:
>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.
> 
>> +
>> +  clocks:
>> +    maxItems: 1
>> +    description: RTC counter clock
> 
> Just items: with description instead.
> 

OK

>> +
>> +  clock-names:
>> +    maxItems: 1
> 
> Nope, it must be specifc. Or just drop. This applies to all your patches.

OK

> 
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - interrupt-names
>> +  - clocks
>> +  - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +    rtc: rtc@1004ec00 {
> 
> Drop label, not used.

OK

> 
>> +        compatible = "renesas,rzg3s-rtc";
>> +        reg = <0x1004ec00 0x400>;
>> +        interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
>> +        interrupt-names = "alarm", "period", "carry";
>> +        clocks = <&vbattclk>;
>> +        clock-names = "counter";
>> +        status = "disabled";
> 
> Why do you paste it eevrywhere? It does no really make sense.

Not sure. I'll drop it.

Thank you for your review,
Claudiu Beznea

> 
> Best regards,
> Krzysztof
> 

Re: [PATCH 06/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC

[Alexandre Belloni]

On 14/06/2024 14:06:38+0300, claudiu beznea wrote:
> >> +	/*
> >> +	 * Stop the RTC and set to 12 hours mode and calendar count mode.
> >> +	 * RCR2.START initial value is undefined so we need to stop here
> >> +	 * all the time.
> >> +	 */
> > 
> > Certainly not, if you stop the RTC on probe, you lose the time
> > information, this must only be done when the RTC has never been
> > initialised. The whole goal of the RTC is the keep time across reboots,
> > its lifecycle is longer than the system.
> 
> This was also my first thought when I read the HW manual.
> 
> It has been done like this to follow the HW manual. According to HW manual
> [1], chapter 22.3.19 RTC Control Register 2 (RCR2), initial value of START
> bit is undefined.
> 
> If it's 1 while probing but it has never been initialized, we can falsely
> detect that RTC is started and skip the rest of the initialization steps.
> W/o initialization configuration, the RTC will not be able to work.
> 
> Even with this implementation we don't loose the time b/w reboots. Here is
> the output on my board [2]. The steps I did were the following:
> 1/ remove the power to the board (I don't have a battery for RTC installed
>    at the moment)
> 2/ boot the board and issue hwclock -w
> 3/ reboot
> 4/ check the systime and rtc time
> 5/ poweroff
> 6/ poweron
> 7/ boot and check systime and RTC time
> 
> As you can see the time is not lost but continue to increment. I presume
> the hardware takes into account that time needs to increment when initial
> configuration is executed.

I don't think so, I guess it stops ticking but the registers are not
reset so when ts starts ticking again, you are not too far from the time
that it should report.

> 
> [1]
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250
> [2] https://p.fr33tux.org/585cd6
> 
> > 
> > Also, why do you insist on 12H-mode? The proper thing to do is to support
> > 12H-mode on read but always use 24H-mode when setting the time.
> 
> OK, I wasn't aware of this. I think I followed this approach as it looked
> to me the number of operation to update the hardware registers was lower
> for 12h mode.

How come, using 12H-mode implies testing for the AM/PM bit and doing and
addition while 24H-mode would simply be a read?

> >> +	priv->rtc_dev->ops = &rtca3_ops;
> >> +	priv->rtc_dev->max_user_freq = 256;
> >> +	priv->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0);
> >> +	priv->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59);
> > 
> > This very much looks like the range should be 2000 to 2099, why do you
> > want to shift it?
> 
> 2000-2099 was my first option for this but then I saw one of your old
> commits on this topic and, since I'm not very familiar with RTC,
> I took it as example. I'll adjust as you proposed.
> 
> commit beee05dfbead
> Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
> Date:   Wed Mar 20 12:30:10 2019 +0100
> 
>     rtc: sh: set range
> 
>     The SH RTC is a BCD RTC with some version having 4 digits for the year.
> 
>     The range for the RTCs with only 2 digits for the year was unfortunately
>     shifted to handle 1999 to 2098.
> 
>     Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>     Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

This is because the sh driver predated the introduction of the range and
was already shifting it.


-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH 03/12] dt-bindings: mfd: renesas,rzg3s-vbattb: Document VBATTB

[claudiu beznea]

On 17.06.2024 10:16, claudiu beznea wrote:
> 
> 
> On 16.06.2024 10:38, Krzysztof Kozlowski wrote:
>> On 14/06/2024 09:19, Claudiu wrote:
>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>>> +
>>> +maintainers:
>>> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - const: renesas,rzg3s-vbattb
>>> +      - const: syscon
>>> +      - const: simple-mfd
>>
>> No, mfd does no look good. That's not a simple device anymore and you
>> claim here child does not need vbat bclk, power domains and resets? That
>> would be a big surprise, although technically possible.
> 
> I wasn't sure how this MFD will be received by the Renesas maintainers so I
> kept it simple for this version.
> 
> In theory the VBAT clk, power domain and resets are specific to VBAT module
> itself but, indeed, the child cannot work w/o these.
> 
>>
>> Please clarify: which of parent resources are needed for children?
> 
> VBAT clock, power domain are needed. Reset, too. In the current
> implementation the reset is deasserted though parent by calling the
> syscon_node_to_regmap(np->parent) in the clock driver.
> 
>>
>> ...
>>
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +    vbattb: vbattb@1005c000 {
>>> +        compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
>>> +        reg = <0x1005c000 0x1000>;
>>> +        ranges = <0 0 0x1005c000 0 0x1000>;
>>> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>>> +        interrupt-names = "tampdi";
>>> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
>>> +        clock-names = "bclk";
>>> +        power-domains = <&cpg>;
>>> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
>>> +        #address-cells = <2>;
>>> +        #size-cells = <2>;
>>> +        status = "disabled";
>>
>> Drop
> 
> Could you please clarify this? Would you want me to drop the full node
> (same for clock-controller node)?

Looking at your review on patch 05/12 from this series I noticed you're
taking about the status = "disabled" lines.

I'll drop it as suggested.

Thank you,
Claudiu Beznea

> 
> Can you point me an example that you are thinking about?
> 
> Thank you,
> Claudiu Beznea
> 
>>
>>> +
>>> +        vbattclk: clock-controller@1c {
>>> +            compatible = "renesas,rzg3s-vbattb-clk";
>>> +            reg = <0 0x1c 0 0x10>;
>>> +            clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
>>> +            clock-names = "bclk", "vbattb_xtal";
>>> +            #clock-cells = <0>;
>>> +            power-domains = <&cpg>;
>>> +            status = "disabled";
>>
>> Drop
>>
>>> +        };
>>> +    };
>>> +
>>> +...
>>
>> Best regards,
>> Krzysztof
>>

Re: [PATCH 06/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC

[claudiu beznea]

On 17.06.2024 10:25, Alexandre Belloni wrote:
> On 14/06/2024 14:06:38+0300, claudiu beznea wrote:
>>>> +	/*
>>>> +	 * Stop the RTC and set to 12 hours mode and calendar count mode.
>>>> +	 * RCR2.START initial value is undefined so we need to stop here
>>>> +	 * all the time.
>>>> +	 */
>>>
>>> Certainly not, if you stop the RTC on probe, you lose the time
>>> information, this must only be done when the RTC has never been
>>> initialised. The whole goal of the RTC is the keep time across reboots,
>>> its lifecycle is longer than the system.
>>
>> This was also my first thought when I read the HW manual.
>>
>> It has been done like this to follow the HW manual. According to HW manual
>> [1], chapter 22.3.19 RTC Control Register 2 (RCR2), initial value of START
>> bit is undefined.
>>
>> If it's 1 while probing but it has never been initialized, we can falsely
>> detect that RTC is started and skip the rest of the initialization steps.
>> W/o initialization configuration, the RTC will not be able to work.
>>
>> Even with this implementation we don't loose the time b/w reboots. Here is
>> the output on my board [2]. The steps I did were the following:
>> 1/ remove the power to the board (I don't have a battery for RTC installed
>>    at the moment)
>> 2/ boot the board and issue hwclock -w
>> 3/ reboot
>> 4/ check the systime and rtc time
>> 5/ poweroff
>> 6/ poweron
>> 7/ boot and check systime and RTC time
>>
>> As you can see the time is not lost but continue to increment. I presume
>> the hardware takes into account that time needs to increment when initial
>> configuration is executed.
> 
> I don't think so, I guess it stops ticking but the registers are not
> reset so when ts starts ticking again, you are not too far from the time
> that it should report.

I'll double check with hardware team on this and return with an answer.

Thank you for your review,
Claudiu Beznea

> 
>>
>> [1]
>> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250
>> [2] https://p.fr33tux.org/585cd6
>>
>>>
>>> Also, why do you insist on 12H-mode? The proper thing to do is to support
>>> 12H-mode on read but always use 24H-mode when setting the time.
>>
>> OK, I wasn't aware of this. I think I followed this approach as it looked
>> to me the number of operation to update the hardware registers was lower
>> for 12h mode.
> 
> How come, using 12H-mode implies testing for the AM/PM bit and doing and
> addition while 24H-mode would simply be a read?
> 
>>>> +	priv->rtc_dev->ops = &rtca3_ops;
>>>> +	priv->rtc_dev->max_user_freq = 256;
>>>> +	priv->rtc_dev->range_min = mktime64(1999, 1, 1, 0, 0, 0);
>>>> +	priv->rtc_dev->range_max = mktime64(2098, 12, 31, 23, 59, 59);
>>>
>>> This very much looks like the range should be 2000 to 2099, why do you
>>> want to shift it?
>>
>> 2000-2099 was my first option for this but then I saw one of your old
>> commits on this topic and, since I'm not very familiar with RTC,
>> I took it as example. I'll adjust as you proposed.
>>
>> commit beee05dfbead
>> Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
>> Date:   Wed Mar 20 12:30:10 2019 +0100
>>
>>     rtc: sh: set range
>>
>>     The SH RTC is a BCD RTC with some version having 4 digits for the year.
>>
>>     The range for the RTCs with only 2 digits for the year was unfortunately
>>     shifted to handle 1999 to 2098.
>>
>>     Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>     Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> 
> This is because the sh driver predated the introduction of the range and
> was already shifting it.
> 
> 

Re: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver

[claudiu beznea]

On 16.06.2024 10:38, Krzysztof Kozlowski wrote:
> On 14/06/2024 09:19, Claudiu wrote:
>> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +    vbattb: vbattb@1005c000 {
>> +        compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
>> +        reg = <0x1005c000 0x1000>;
>> +        ranges = <0 0 0x1005c000 0 0x1000>;
>> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>> +        interrupt-names = "tampdi";
>> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
>> +        clock-names = "bclk";
>> +        power-domains = <&cpg>;
>> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +        status = "disabled";
> 
> Drop.

OK.

> 
> And keep only one complete example, instead of two. See other complex
> devices as example.
Do you have in mind an example that you can point me to?

Thank you,
Claudiu Beznea

> 
> 
> Best regards,
> Krzysztof
> 

Re: [PATCH 03/12] dt-bindings: mfd: renesas,rzg3s-vbattb: Document VBATTB

[Krzysztof Kozlowski]

On 17/06/2024 09:16, claudiu beznea wrote:
> 
> 
> On 16.06.2024 10:38, Krzysztof Kozlowski wrote:
>> On 14/06/2024 09:19, Claudiu wrote:
>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>
>>> +
>>> +maintainers:
>>> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    items:
>>> +      - const: renesas,rzg3s-vbattb
>>> +      - const: syscon
>>> +      - const: simple-mfd
>>
>> No, mfd does no look good. That's not a simple device anymore and you
>> claim here child does not need vbat bclk, power domains and resets? That
>> would be a big surprise, although technically possible.
> 
> I wasn't sure how this MFD will be received by the Renesas maintainers so I
> kept it simple for this version.
> 
> In theory the VBAT clk, power domain and resets are specific to VBAT module
> itself but, indeed, the child cannot work w/o these.
> 
>>
>> Please clarify: which of parent resources are needed for children?
> 
> VBAT clock, power domain are needed. Reset, too. In the current
> implementation the reset is deasserted though parent by calling the
> syscon_node_to_regmap(np->parent) in the clock driver.

Then you must drop simple-mfd. It's not simple-mfd if children needs
parent's resources.

> 
>>
>> ...
>>
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/clock/r9a08g045-cpg.h>
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> +    vbattb: vbattb@1005c000 {
>>> +        compatible = "renesas,rzg3s-vbattb", "syscon", "simple-mfd";
>>> +        reg = <0x1005c000 0x1000>;
>>> +        ranges = <0 0 0x1005c000 0 0x1000>;
>>> +        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
>>> +        interrupt-names = "tampdi";
>>> +        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>;
>>> +        clock-names = "bclk";
>>> +        power-domains = <&cpg>;
>>> +        resets = <&cpg R9A08G045_VBAT_BRESETN>;
>>> +        #address-cells = <2>;
>>> +        #size-cells = <2>;
>>> +        status = "disabled";
>>
>> Drop
> 
> Could you please clarify this? Would you want me to drop the full node
> (same for clock-controller node)?
> 
> Can you point me an example that you are thinking about?

The exact line I commented under.

There is never status in any example. Please open any other binding or
example-schema.



Best regards,
Krzysztof

Re: [PATCH 05/12] dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RZ/G3S RTC

[Conor Dooley]

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On Mon, Jun 17, 2024 at 10:19:55AM +0300, claudiu beznea wrote:
> 
> 
> On 15.06.2024 15:20, Conor Dooley wrote:
> > On Fri, Jun 14, 2024 at 10:19:25AM +0300, Claudiu wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> ---
> >>  .../bindings/rtc/renesas,rzg3s-rtc.yaml       | 60 +++++++++++++++++++
> >>  1 file changed, 60 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> >> new file mode 100644
> >> index 000000000000..0e17f8a36155
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/rtc/renesas,rzg3s-rtc.yaml
> >> @@ -0,0 +1,60 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/rtc/renesas,rzg3s-rtc.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: Real Time Clock for Renesas RZ/G3S SoC
> >> +
> >> +maintainers:
> >> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> +
> > 
> > Missing a ref to adc.yaml,
> 
> I guess you mean rtc.yaml?
> 
> I missed that rtc.yaml. I'll update it.

iio on my brain, I did indeed mean rtc.yaml.

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Re: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver

[Conor Dooley]

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On Mon, Jun 17, 2024 at 10:02:47AM +0300, claudiu beznea wrote:
> 
> 
> On 15.06.2024 15:17, Conor Dooley wrote:
> > On Fri, Jun 14, 2024 at 10:19:22AM +0300, Claudiu wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>
> >> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feeds
> >> the RTC and the tamper detector. Add documentation for the VBATTB clock
> >> driver.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> ---
> >>  .../clock/renesas,rzg3s-vbattb-clk.yaml       | 90 +++++++++++++++++++
> >>  1 file changed, 90 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
> >> new file mode 100644
> >> index 000000000000..ef52a0c0f874
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
> >> @@ -0,0 +1,90 @@
> >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/clock/renesas,rzg3s-vbattb-clk.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: Renesas VBATTB clock
> >> +
> >> +maintainers:
> >> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >> +
> >> +description:
> >> +  Renesas VBATTB module is an always on powered module (backed by battery) which
> >> +  generates a clock (VBATTCLK). This clocks feeds the RTC and the tamper detector
> >> +  modules.
> >> +
> >> +properties:
> >> +  compatible:
> >> +    const: renesas,rzg3s-vbattb-clk
> >> +
> >> +  reg:
> >> +    maxItems: 1
> >> +
> >> +  clocks:
> >> +    items:
> >> +      - description: VBATTB module clock
> >> +      - description: VBATTB input xtal
> >> +
> >> +  clock-names:
> >> +    items:
> >> +      - const: bclk
> >> +      - const: vbattb_xtal
> >> +
> >> +  '#clock-cells':
> >> +    const: 0
> >> +
> >> +  power-domains:
> >> +    maxItems: 1
> >> +
> >> +  renesas,vbattb-load-nanofarads:
> >> +    description: load capacitance of the on board xtal
> >> +    $ref: /schemas/types.yaml#/definitions/uint32
> >> +    enum: [ 4000, 7000, 9000, 12500 ]
> >> +
> >> +  renesas,vbattb-osc-bypass:
> >> +    description: set when external clock is connected to RTXOUT pin
> >> +    type: boolean
> > 
> > When you say "external clock", is that an input or an output?
> 
> I took that statement from the HW manual. As of the HW manual [1], table
> 42.2, that would be an input.

Forgive me for not wanting to open the zip etc and find the information
in the document, but why do you need an extra property? Is it not
something you can determine from the clocks/clock-names properties?
It sounds like an additional clock from your description, is it actually
different way to provide the second clock you mention above?

> 
> [1]
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250
> 

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Re: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver

[claudiu beznea]

On 17.06.2024 18:19, Conor Dooley wrote:
> On Mon, Jun 17, 2024 at 10:02:47AM +0300, claudiu beznea wrote:
>>
>>
>> On 15.06.2024 15:17, Conor Dooley wrote:
>>> On Fri, Jun 14, 2024 at 10:19:22AM +0300, Claudiu wrote:
>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>
>>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feeds
>>>> the RTC and the tamper detector. Add documentation for the VBATTB clock
>>>> driver.
>>>>
>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>> ---
>>>>  .../clock/renesas,rzg3s-vbattb-clk.yaml       | 90 +++++++++++++++++++
>>>>  1 file changed, 90 insertions(+)
>>>>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
>>>> new file mode 100644
>>>> index 000000000000..ef52a0c0f874
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
>>>> @@ -0,0 +1,90 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/clock/renesas,rzg3s-vbattb-clk.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Renesas VBATTB clock
>>>> +
>>>> +maintainers:
>>>> +  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>> +
>>>> +description:
>>>> +  Renesas VBATTB module is an always on powered module (backed by battery) which
>>>> +  generates a clock (VBATTCLK). This clocks feeds the RTC and the tamper detector
>>>> +  modules.
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    const: renesas,rzg3s-vbattb-clk
>>>> +
>>>> +  reg:
>>>> +    maxItems: 1
>>>> +
>>>> +  clocks:
>>>> +    items:
>>>> +      - description: VBATTB module clock
>>>> +      - description: VBATTB input xtal
>>>> +
>>>> +  clock-names:
>>>> +    items:
>>>> +      - const: bclk
>>>> +      - const: vbattb_xtal
>>>> +
>>>> +  '#clock-cells':
>>>> +    const: 0
>>>> +
>>>> +  power-domains:
>>>> +    maxItems: 1
>>>> +
>>>> +  renesas,vbattb-load-nanofarads:
>>>> +    description: load capacitance of the on board xtal
>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>> +    enum: [ 4000, 7000, 9000, 12500 ]
>>>> +
>>>> +  renesas,vbattb-osc-bypass:
>>>> +    description: set when external clock is connected to RTXOUT pin
>>>> +    type: boolean
>>>
>>> When you say "external clock", is that an input or an output?
>>
>> I took that statement from the HW manual. As of the HW manual [1], table
>> 42.2, that would be an input.
> 
> Forgive me for not wanting to open the zip etc and find the information
> in the document, but why do you need an extra property? Is it not
> something you can determine from the clocks/clock-names properties?

It can't be determined from clocks/clock-names as of my understanding. It
depends on the type of the input clock (crystal oscillator or external
hardware device generating the clock).

> It sounds like an additional clock from your description, is it actually
> different way to provide the second clock you mention above?

This is the block diagram (see [1], only picture this time) of the module
controlling the clock. Please open it, it helps in understanding what I'll
explain above.

The VBATTB blocks controlling the VBATTBCLK are:
- 32KHz-clock oscillator
- the mux controlled by BKSCCR.SOSEL
- the gate who's input is the mux output and XOSCCR.OUTEN

To the 32 KHz-clock oscillator block could be connected:
1/ either a crystal oscillator in which case it will be connected to both
RTXIN and RTXOUT pins (the direction of RTXOUT is wrong in this picture for
this case)
2/ or a device (like [2]) generating a clock which has a single output and,
from my understanding and experience with devices like this, only RTXIN is
needed, RTXOUT is connected to the ground; for this case the 32KHz-clock
oscillator block from [1] need to be bypassed in which case the newly
introduced property will be used; this will select the XBYP on the mux.

Thank you,
Claudiu Beznea

[1] https://pasteboard.co/QYsCvhfQlX6n.png
[2]
https://ro.mouser.com/datasheet/2/268/DSC1001_3_4_1_8V_3_3V_Low_Power_Precision_CMOS_Osc-3314582.pdf

> 
>>
>> [1]
>> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzg3s-general-purpose-microprocessors-single-core-arm-cortex-a55-11-ghz-cpu-and-dual-core-cortex-m33-250
>>

Re: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver

[Geert Uytterhoeven]

Hi Claudiu,

On Tue, Jun 18, 2024 at 9:34 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
> On 17.06.2024 18:19, Conor Dooley wrote:
> > On Mon, Jun 17, 2024 at 10:02:47AM +0300, claudiu beznea wrote:
> >> On 15.06.2024 15:17, Conor Dooley wrote:
> >>> On Fri, Jun 14, 2024 at 10:19:22AM +0300, Claudiu wrote:
> >>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>>
> >>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feeds
> >>>> the RTC and the tamper detector. Add documentation for the VBATTB clock
> >>>> driver.
> >>>>
> >>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >>>> ---
> >>>>  .../clock/renesas,rzg3s-vbattb-clk.yaml       | 90 +++++++++++++++++++
> >>>>  1 file changed, 90 insertions(+)
> >>>>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
> >>>> new file mode 100644
> >>>> index 000000000000..ef52a0c0f874
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
> >>>> +  renesas,vbattb-osc-bypass:
> >>>> +    description: set when external clock is connected to RTXOUT pin

FTR, this contradicts the explanation below, which states the external
clock oscillator is connected to RTXIN.

> >>>> +    type: boolean
> >>>
> >>> When you say "external clock", is that an input or an output?
> >>
> >> I took that statement from the HW manual. As of the HW manual [1], table
> >> 42.2, that would be an input.
> >
> > Forgive me for not wanting to open the zip etc and find the information
> > in the document, but why do you need an extra property? Is it not
> > something you can determine from the clocks/clock-names properties?
>
> It can't be determined from clocks/clock-names as of my understanding. It
> depends on the type of the input clock (crystal oscillator or external
> hardware device generating the clock).
>
> > It sounds like an additional clock from your description, is it actually
> > different way to provide the second clock you mention above?
>
> This is the block diagram (see [1], only picture this time) of the module
> controlling the clock. Please open it, it helps in understanding what I'll
> explain above.
>
> The VBATTB blocks controlling the VBATTBCLK are:
> - 32KHz-clock oscillator
> - the mux controlled by BKSCCR.SOSEL
> - the gate who's input is the mux output and XOSCCR.OUTEN
>
> To the 32 KHz-clock oscillator block could be connected:
> 1/ either a crystal oscillator in which case it will be connected to both
> RTXIN and RTXOUT pins (the direction of RTXOUT is wrong in this picture for
> this case)
> 2/ or a device (like [2]) generating a clock which has a single output and,
> from my understanding and experience with devices like this, only RTXIN is
> needed, RTXOUT is connected to the ground; for this case the 32KHz-clock
> oscillator block from [1] need to be bypassed in which case the newly
> introduced property will be used; this will select the XBYP on the mux.

Sounds similar to the RAA215300 PMIC, which includes an ISL1208-derived
RTC, where this was handled using two different clock names:
https://elixir.bootlin.com/linux/v6.10-rc1/source/Documentation/devicetree/bindings/regulator/renesas,raa215300.yaml#L49
https://elixir.bootlin.com/linux/v6.10-rc1/source/drivers/rtc/rtc-isl1208.c#L869

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 02/12] dt-bindings: clock: renesas,rzg3s-vbattb-clk: Document the VBATTB clock driver

[claudiu beznea]

Hi, Geert,

On 18.06.2024 10:56, Geert Uytterhoeven wrote:
> Hi Claudiu,
> 
> On Tue, Jun 18, 2024 at 9:34 AM claudiu beznea <claudiu.beznea@tuxon.dev> wrote:
>> On 17.06.2024 18:19, Conor Dooley wrote:
>>> On Mon, Jun 17, 2024 at 10:02:47AM +0300, claudiu beznea wrote:
>>>> On 15.06.2024 15:17, Conor Dooley wrote:
>>>>> On Fri, Jun 14, 2024 at 10:19:22AM +0300, Claudiu wrote:
>>>>>> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>>
>>>>>> The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that feeds
>>>>>> the RTC and the tamper detector. Add documentation for the VBATTB clock
>>>>>> driver.
>>>>>>
>>>>>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>>>>>> ---
>>>>>>  .../clock/renesas,rzg3s-vbattb-clk.yaml       | 90 +++++++++++++++++++
>>>>>>  1 file changed, 90 insertions(+)
>>>>>>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
>>>>>> new file mode 100644
>>>>>> index 000000000000..ef52a0c0f874
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg3s-vbattb-clk.yaml
>>>>>> +  renesas,vbattb-osc-bypass:
>>>>>> +    description: set when external clock is connected to RTXOUT pin
> 
> FTR, this contradicts the explanation below, which states the external
> clock oscillator is connected to RTXIN.

I agree.

> 
>>>>>> +    type: boolean
>>>>>
>>>>> When you say "external clock", is that an input or an output?
>>>>
>>>> I took that statement from the HW manual. As of the HW manual [1], table
>>>> 42.2, that would be an input.
>>>
>>> Forgive me for not wanting to open the zip etc and find the information
>>> in the document, but why do you need an extra property? Is it not
>>> something you can determine from the clocks/clock-names properties?
>>
>> It can't be determined from clocks/clock-names as of my understanding. It
>> depends on the type of the input clock (crystal oscillator or external
>> hardware device generating the clock).
>>
>>> It sounds like an additional clock from your description, is it actually
>>> different way to provide the second clock you mention above?
>>
>> This is the block diagram (see [1], only picture this time) of the module
>> controlling the clock. Please open it, it helps in understanding what I'll
>> explain above.
>>
>> The VBATTB blocks controlling the VBATTBCLK are:
>> - 32KHz-clock oscillator
>> - the mux controlled by BKSCCR.SOSEL
>> - the gate who's input is the mux output and XOSCCR.OUTEN
>>
>> To the 32 KHz-clock oscillator block could be connected:
>> 1/ either a crystal oscillator in which case it will be connected to both
>> RTXIN and RTXOUT pins (the direction of RTXOUT is wrong in this picture for
>> this case)
>> 2/ or a device (like [2]) generating a clock which has a single output and,
>> from my understanding and experience with devices like this, only RTXIN is
>> needed, RTXOUT is connected to the ground; for this case the 32KHz-clock
>> oscillator block from [1] need to be bypassed in which case the newly
>> introduced property will be used; this will select the XBYP on the mux.
> 
> Sounds similar to the RAA215300 PMIC, which includes an ISL1208-derived
> RTC, where this was handled using two different clock names:
> https://elixir.bootlin.com/linux/v6.10-rc1/source/Documentation/devicetree/bindings/regulator/renesas,raa215300.yaml#L49
> https://elixir.bootlin.com/linux/v6.10-rc1/source/drivers/rtc/rtc-isl1208.c#L869

Yes, seem similar. I wasn't aware of this approach. I'll switch to it.

Thank  you,
Claudiu Beznea

> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 

Re: [PATCH 01/12] clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP

[Geert Uytterhoeven]

On Fri, Jun 14, 2024 at 9:19 AM Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB)
> that generates the RTC clock. Add clock, reset and power domain support
> for it.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.11.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 06/12] rtc: renesas-rtca3: Add driver for RTCA-3 available on Renesas RZ/G3S SoC

[claudiu beznea]

Hi, Alexandre,

On 17.06.2024 10:31, claudiu beznea wrote:
> On 17.06.2024 10:25, Alexandre Belloni wrote:
>> On 14/06/2024 14:06:38+0300, claudiu beznea wrote:
>>>>> +	/*
>>>>> +	 * Stop the RTC and set to 12 hours mode and calendar count mode.
>>>>> +	 * RCR2.START initial value is undefined so we need to stop here
>>>>> +	 * all the time.
>>>>> +	 */
>>>> Certainly not, if you stop the RTC on probe, you lose the time
>>>> information, this must only be done when the RTC has never been
>>>> initialised. The whole goal of the RTC is the keep time across reboots,
>>>> its lifecycle is longer than the system.
>>> This was also my first thought when I read the HW manual.
>>>
>>> It has been done like this to follow the HW manual. According to HW manual
>>> [1], chapter 22.3.19 RTC Control Register 2 (RCR2), initial value of START
>>> bit is undefined.
>>>
>>> If it's 1 while probing but it has never been initialized, we can falsely
>>> detect that RTC is started and skip the rest of the initialization steps.
>>> W/o initialization configuration, the RTC will not be able to work.
>>>
>>> Even with this implementation we don't loose the time b/w reboots. Here is
>>> the output on my board [2]. The steps I did were the following:
>>> 1/ remove the power to the board (I don't have a battery for RTC installed
>>>    at the moment)
>>> 2/ boot the board and issue hwclock -w
>>> 3/ reboot
>>> 4/ check the systime and rtc time
>>> 5/ poweroff
>>> 6/ poweron
>>> 7/ boot and check systime and RTC time
>>>
>>> As you can see the time is not lost but continue to increment. I presume
>>> the hardware takes into account that time needs to increment when initial
>>> configuration is executed.
>> I don't think so, I guess it stops ticking but the registers are not
>> reset so when ts starts ticking again, you are not too far from the time
>> that it should report.
> I'll double check with hardware team on this and return with an answer.

It has been confirmed me that the HW manual has a mistake and we can avoid
stopping the RTC here every time. I'll adjust it in the next version.

Thank you,
Claudiu Beznea