From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8914C25B74 for ; Thu, 16 May 2024 05:38:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gODirNdJ4m7FJ4vpgReEJrikm5u3kd5hSRVJAdFHuAE=; b=mogOAIVDvwwauK CGsvVMfqKChb2popgOJLL1KuTsc/47kql0DdY7Gj5Nz4vq5fbVKjVxiKWivXV2ho4tXHQKgYgd3uN +ZOFHs0VHl+Wi6L9JEUZ2gYWjS/QcCK8+fyR7dHHZGkMfBKePTe6vZD45GFh0Z5yo7Eiyh8LyuNar yVudevVfceO1S9nu1If/ZeZllqICU275KKvrOyWCz8yAhkhkMaN0fjEobpuwQwb/7kGCMm+V1qx9t lLivVn9/QC0o749aK6eSKcgSD1JcgDY0ARIiSGHqQ5Dlqk4lPjG/hY1qqTNm9XtJQMSDoybqKBnVA aW7grejuJLrTI2BEfOmA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7ToR-00000003mRi-2dry; Thu, 16 May 2024 05:37:55 +0000 Received: from lelv0142.ext.ti.com ([198.47.23.249]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s7ToO-00000003mQm-1aqb for linux-arm-kernel@lists.infradead.org; Thu, 16 May 2024 05:37:54 +0000 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 44G5bTiY107053; Thu, 16 May 2024 00:37:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1715837849; bh=Y+0+gVcTYlTJ4NuM6emf0ej+bmnF17XCG4Y5MCExeEM=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=M0fIfb+vug0ndmHZykTjjoy+wJnfkyjq5jD7Zk9UPyIXNuJooZJbfUKs1yR41eR4h 1Zc3eAm8Dj8wh5bETHru5KCxzrUZ39tKExNVgtPnB9NJH6ee1tzqSLpz18GZyu85wO uDJJ9Hcx7qRwOzSH/77e6PQ8RBlzHaZjOcMH+4iw= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 44G5bTS3063310 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 16 May 2024 00:37:29 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 16 May 2024 00:37:28 -0500 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 16 May 2024 00:37:28 -0500 Received: from localhost (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 44G5bSjM068377; Thu, 16 May 2024 00:37:28 -0500 Date: Thu, 16 May 2024 11:07:27 +0530 From: Siddharth Vadapalli To: Bjorn Helgaas CC: Siddharth Vadapalli , , , , , , , , , , , , , , Subject: Re: [PATCH v7 2/2] PCI: keystone: Fix pci_ops for AM654x SoC Message-ID: References: <20240514211452.GA2082543@bhelgaas> <20240515192614.GA2133406@bhelgaas> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240515192614.GA2133406@bhelgaas> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240515_223752_659710_D1327478 X-CRM114-Status: GOOD ( 32.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 15, 2024 at 02:26:14PM -0500, Bjorn Helgaas wrote: > On Tue, May 14, 2024 at 04:14:54PM -0500, Bjorn Helgaas wrote: > > On Tue, May 14, 2024 at 05:41:48PM +0530, Siddharth Vadapalli wrote: > > > On Mon, May 13, 2024 at 04:53:50PM -0500, Bjorn Helgaas wrote: > > ... > > > > > I'm not quite clear on the mechanism, but it would be helpful to at > > > > least know what's wrong and on what platform. E.g., currently v4.90 > > > > suffers Completion Timeouts and 45 second boot delays? And this patch > > > > fixes that? > > > > > > Yes, the Completion Timeouts cause the 45 second boot delays and this > > > patch fixes that. > > > > And this problem happens on AM654x/v4.90a, right? I really want the > > commit log to say what platform is affected! > > > > Maybe something like this? > > > > PCI: keystone: Enable BAR 0 only for v3.65a > > > > The BAR 0 initialization done by ks_pcie_v3_65_add_bus() should > > happen for v3.65a devices only. On other devices, BAR 0 should be > > left disabled, as it is by dw_pcie_setup_rc(). > > > > After 6ab15b5e7057 ("PCI: dwc: keystone: Convert .scan_bus() > > callback to use add_bus"), ks_pcie_v3_65_add_bus() enabled BAR 0 for > > both v3.65a and v4.90a devices. On the AM654x SoC, which uses > > v4.90a, enabling BAR 0 causes Completion Timeouts when setting up > > MSI-X. These timeouts delay boot of the AM654x by about 45 seconds. > > > > Move the BAR 0 initialization to ks_pcie_msi_host_init(), which is > > only used for v3.65a devices, and remove ks_pcie_v3_65_add_bus(). > > I haven't heard anything so I amended it to the above. But please > correct me if it's wrong. I would suggest specifying the failing combination since I do not know if there is another device that is using v4.90a but doesn't see this issue. What is certain is that this issue is seen with the v4.90a controller on AM654x platform. Despite the PCIe Controller version remaining the same across different platforms, it might be possible that not all features supported by the PCIe Controller are enabled on all platforms. For that reason, it appears to me that the subject could be: PCI: keystone: Don't enable BAR 0 for AM654x which implicitly indicates the combination as well (v4.90a on AM654x). The commit message's contents could be reduced to: After 6ab15b5e7057 ("PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus"), ks_pcie_v3_65_add_bus() enabled BAR 0 for both v3.65a and v4.90a devices. On the AM654x SoC, which uses v4.90a, enabling BAR 0 causes Completion Timeouts when setting up MSI-X. These timeouts delay boot of the AM654x by about 45 seconds. Move the BAR 0 initialization to ks_pcie_msi_host_init(), which is only used for v3.65a devices, and remove ks_pcie_v3_65_add_bus(). by dropping: The BAR 0 initialization done by ks_pcie_v3_65_add_bus() should happen for v3.65a devices only. On other devices, BAR 0 should be left disabled, as it is by dw_pcie_setup_rc(). The reason behind dropping the above paragraph is that BAR 0 could probably be enabled on other controller versions as well, but not on the v4.90a controller on the AM654x SoC. Thank you Bjorn, for enhancing the commit message. Regards, Siddharth. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel