From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38407C433E0 for ; Thu, 18 Jun 2020 10:50:21 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 065F8206E2 for ; Thu, 18 Jun 2020 10:50:21 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="R9xq/c1W" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 065F8206E2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description :Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mpVRYloSMcL2tVnaDEoArg93eQO+xmir9q1zLv4F9UQ=; b=R9xq/c1WjbkIuC F9I8t+soVf6LEu06IIW6+rCMwj94fDKpEzZo/9XAUxynPeUsJM56l0KoPiGaTj4AgdV3sxwhbFEeN r7IG/CMomm1efcXHuq4Op89pDFetflugWn3KEPDg9vqc39H6qSfXNQ8qY8dTB+BPiFYeumSKUoxRf IIAu78vvYaeTncd8ebRMGBp6EFXgddGhH2Lkcuy1zchKkXwVT+XIIAG82w+yb8UT8EZkSaev1nohI zkwXyROpZbeKUdZroxWY5ihZzdUNpg1yyJwmZkkgNwO07Y5HAMTKL8HBjrh5zJ+/eurZdYOBG8ZWz 0RHBNEAAKyl0YkdnZRLg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jls7g-0005dp-LD; Thu, 18 Jun 2020 10:50:20 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jls7e-0005d2-3F for linux-arm-kernel@lists.infradead.org; Thu, 18 Jun 2020 10:50:19 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 85C5431B; Thu, 18 Jun 2020 03:50:14 -0700 (PDT) Received: from [192.168.0.110] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9935A3F71F; Thu, 18 Jun 2020 03:50:12 -0700 (PDT) Subject: Re: [PATCH v5 1/7] arm64: perf: Add missing ISB in armv8pmu_enable_event() To: Stephen Boyd , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20200617113851.607706-1-alexandru.elisei@arm.com> <20200617113851.607706-2-alexandru.elisei@arm.com> <159242406774.62212.13909672383879587787@swboyd.mtv.corp.google.com> From: Alexandru Elisei Message-ID: Date: Thu, 18 Jun 2020 11:50:51 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <159242406774.62212.13909672383879587787@swboyd.mtv.corp.google.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200618_035018_181280_F2BA824D X-CRM114-Status: GOOD ( 16.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, will@kernel.org, Julien Thierry , Peter Zijlstra , maz@kernel.org, Will Deacon , Arnaldo Carvalho de Melo , Alexander Shishkin , Ingo Molnar , catalin.marinas@arm.com, Namhyung Kim , Jiri Olsa , Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Stephen, Thank you very much for taking the time to review the patches! Comments below. On 6/17/20 9:01 PM, Stephen Boyd wrote: > Quoting Alexandru Elisei (2020-06-17 04:38:45) >> Writes to the PMXEVTYPER_EL0 register are not self-synchronising. In >> armv8pmu_enable_event(), the PE can reorder configuring the event type >> after we have enabled the counter and the interrupt. This can lead to an >> interrupt being asserted because the of the previous event type that we > 'because the of the' doesn't read properly. Typo on my part, will fix it. > >> were counting, not the one that we've just enabled. >> >> The same rationale applies to writes to the PMINTENSET_EL1 register. The PE >> can reorder enabling the interrupt at any point in the future after we have >> enabled the event. >> >> Prevent both situations from happening by adding an ISB just before we >> enable the event counter. >> >> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c >> index 4d7879484cec..ee180b2a5b39 100644 >> --- a/arch/arm64/kernel/perf_event.c >> +++ b/arch/arm64/kernel/perf_event.c >> @@ -605,6 +605,7 @@ static void armv8pmu_enable_event(struct perf_event *event) >> * Enable interrupt for this counter >> */ >> armv8pmu_enable_event_irq(event); >> + isb(); > Please add a comment before the isb() explaining the situation. Nobody > knows what this is for when reading the code and they don't want to do > git archaeology to figure it out. That's a good idea, I'll do that. Thanks, Alex _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel