From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20E4FC433DF for ; Fri, 31 Jul 2020 09:48:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DC5EA20829 for ; Fri, 31 Jul 2020 09:48:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="bQrV9tKm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DC5EA20829 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=DvRDCQdnDWyszJkAtnobc9lZsQbwaRN/0HjtOexsMrc=; b=bQrV9tKmMNpGMEg0p+kj3dvlg UZGLGepk5hzWnly9EmUD6129fRQc5SodB6yY7eqhsIS3Vrq6e7e2xqdlNmjrE0S+qcmuQMs7skJDq yK2+ZDWUssN+x73wSPEwbUJmdxnupPBVw7VLCD2s4mH8V3D2jk/rk0RnNn3KzlS7cmVLV09ZQjJwT roJcdsJ8npUTQkkUhL3JL1+9uVH3x+9oA4Nr+Hk2idPqB37xkYX8WwsFa+vPNbG+DE6tR7WprLmVx k13rOta6G7VdWBP+fY4qtwPOHYQQhHGUbPzET5H5hc2YwldT7FUgWyqXht6rWJsiSwpIgZ60iu430 BBXPcKR1w==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k1RcR-0004H4-Km; Fri, 31 Jul 2020 09:46:27 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k1RcO-0004Fg-To for linux-arm-kernel@lists.infradead.org; Fri, 31 Jul 2020 09:46:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 40F7E31B; Fri, 31 Jul 2020 02:46:23 -0700 (PDT) Received: from [10.37.12.83] (unknown [10.37.12.83]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EECEE3F718; Fri, 31 Jul 2020 02:46:21 -0700 (PDT) Subject: Re: [RFC PATCH 09/14] coresight: etm4x: Add sysreg access helpers To: mathieu.poirier@linaro.org References: <20200722172040.1299289-1-suzuki.poulose@arm.com> <20200722172040.1299289-10-suzuki.poulose@arm.com> <20200730214110.GF3155687@xps15> From: Suzuki K Poulose Message-ID: Date: Fri, 31 Jul 2020 10:51:08 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: <20200730214110.GF3155687@xps15> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200731_054625_032030_2402C2B4 X-CRM114-Status: GOOD ( 19.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 07/30/2020 10:41 PM, Mathieu Poirier wrote: > On Wed, Jul 22, 2020 at 06:20:35PM +0100, Suzuki K Poulose wrote: >> ETMv4.4 architecture defines the system instructions for accessing >> ETM via register accesses. Add basic support for accessing a given >> register via system instructions. >> >> Cc: Mathieu Poirier >> Cc: Mike Leach >> Signed-off-by: Suzuki K Poulose >> --- >> drivers/hwtracing/coresight/coresight-etm4x.c | 39 ++ >> drivers/hwtracing/coresight/coresight-etm4x.h | 379 ++++++++++++++++-- >> 2 files changed, 394 insertions(+), 24 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c >> static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa) >> { >> /* Writing 0 to TRCOSLAR unlocks the trace registers */ >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >> index 2b51d03ab6d7..f5d708206339 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h 0x1FC >> -/* Resource selection registers */ >> +/* >> + * Resource selection registers, n = 2-31. >> + * First pair (regs 0, 1) is always present and is reserved. >> + */ >> #define TRCRSCTLRn(n) (0x200 + (n * 4)) >> -/* Single-shot comparator registers */ >> +/* Single-shot comparator registers, n = 0-7 */ >> #define TRCSSCCRn(n) (0x280 + (n * 4)) >> #define TRCSSCSRn(n) (0x2A0 + (n * 4)) >> #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) >> @@ -80,11 +83,13 @@ >> #define TRCPDCR 0x310 >> #define TRCPDSR 0x314 >> /* Trace registers (0x318-0xEFC) */ >> -/* Comparator registers */ >> +/* Address Comparator registers n = 0-15 */ >> #define TRCACVRn(n) (0x400 + (n * 8)) >> #define TRCACATRn(n) (0x480 + (n * 8)) >> +/* Data Value Comparator Value registers, n = 0-7 */ >> #define TRCDVCVRn(n) (0x500 + (n * 16)) >> #define TRCDVCMRn(n) (0x580 + (n * 16)) >> +/* ContextID/Virtual ContextID comparators, n = 0-7 */ > > Extra documentation is good but it has to be in a separate patch. > Sure, will split this. It was partly for making sure that I don't miss a case for a register in the list. Cheers Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel