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([2a00:79e0:2e7c:8:7c3d:6070:7e67:29c5]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f12209efsm1739565c88.3.2026.01.05.11.58.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Jan 2026 11:58:30 -0800 (PST) Message-ID: Date: Mon, 5 Jan 2026 11:58:29 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/5] mfd: max77759: add register bitmasks and modify irq configs for charger To: =?UTF-8?Q?Andr=C3=A9_Draszik?= , Sebastian Reichel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Greg Kroah-Hartman , Badhri Jagan Sridharan , Heikki Krogerus , Peter Griffin , Tudor Ambarus , Alim Akhtar Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, RD Babiera , Kyle Tso References: <20251227-max77759-charger-v3-0-54e664f5ca92@google.com> <20251227-max77759-charger-v3-3-54e664f5ca92@google.com> Content-Language: en-US From: Amit Sunil Dhamne In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260105_115835_145098_3C9ECBB7 X-CRM114-Status: GOOD ( 12.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/5/26 8:45 AM, André Draszik wrote: > On Sat, 2025-12-27 at 00:04 +0000, Amit Sunil Dhamne via B4 Relay wrote: >> From: Amit Sunil Dhamne >> >> Add register bitmasks for charger function. >> In addition split the charger IRQs further such that each bit represents >> an IRQ downstream of charger regmap irq chip. In addition populate the >> ack_base to offload irq ack to the regmap irq chip framework. >> >> Signed-off-by: Amit Sunil Dhamne >> --- >>  drivers/mfd/max77759.c       |  91 +++++++++++++++++-- >>  include/linux/mfd/max77759.h | 202 ++++++++++++++++++++++++++++++++++++------- >>  2 files changed, 256 insertions(+), 37 deletions(-) >> >> [...] >> >> diff --git a/include/linux/mfd/max77759.h b/include/linux/mfd/max77759.h >> index c6face34e385..e674a519e782 100644 >> --- a/include/linux/mfd/max77759.h >> +++ b/include/linux/mfd/max77759.h >> @@ -59,35 +59,65 @@ >>  #define MAX77759_MAXQ_REG_AP_DATAIN0            0xb1 >>  #define MAX77759_MAXQ_REG_UIC_SWRST             0xe0 >> >> -#define MAX77759_CHGR_REG_CHG_INT               0xb0 >> -#define MAX77759_CHGR_REG_CHG_INT2              0xb1 >> -#define MAX77759_CHGR_REG_CHG_INT_MASK          0xb2 >> -#define MAX77759_CHGR_REG_CHG_INT2_MASK         0xb3 >> -#define MAX77759_CHGR_REG_CHG_INT_OK            0xb4 >> -#define MAX77759_CHGR_REG_CHG_DETAILS_00        0xb5 >> -#define MAX77759_CHGR_REG_CHG_DETAILS_01        0xb6 >> -#define MAX77759_CHGR_REG_CHG_DETAILS_02        0xb7 >> -#define MAX77759_CHGR_REG_CHG_DETAILS_03        0xb8 >> -#define MAX77759_CHGR_REG_CHG_CNFG_00           0xb9 >> -#define MAX77759_CHGR_REG_CHG_CNFG_01           0xba >> -#define MAX77759_CHGR_REG_CHG_CNFG_02           0xbb >> -#define MAX77759_CHGR_REG_CHG_CNFG_03           0xbc >> -#define MAX77759_CHGR_REG_CHG_CNFG_04           0xbd >> -#define MAX77759_CHGR_REG_CHG_CNFG_05           0xbe >> -#define MAX77759_CHGR_REG_CHG_CNFG_06           0xbf >> -#define MAX77759_CHGR_REG_CHG_CNFG_07           0xc0 >> -#define MAX77759_CHGR_REG_CHG_CNFG_08           0xc1 >> -#define MAX77759_CHGR_REG_CHG_CNFG_09           0xc2 >> -#define MAX77759_CHGR_REG_CHG_CNFG_10           0xc3 >> -#define MAX77759_CHGR_REG_CHG_CNFG_11           0xc4 >> -#define MAX77759_CHGR_REG_CHG_CNFG_12           0xc5 >> -#define MAX77759_CHGR_REG_CHG_CNFG_13           0xc6 >> -#define MAX77759_CHGR_REG_CHG_CNFG_14           0xc7 >> -#define MAX77759_CHGR_REG_CHG_CNFG_15           0xc8 >> -#define MAX77759_CHGR_REG_CHG_CNFG_16           0xc9 >> -#define MAX77759_CHGR_REG_CHG_CNFG_17           0xca >> -#define MAX77759_CHGR_REG_CHG_CNFG_18           0xcb >> -#define MAX77759_CHGR_REG_CHG_CNFG_19           0xcc >> +#define MAX77759_CHGR_REG_CHG_INT                      0xb0 >> +#define   MAX77759_CHGR_REG_CHG_INT_AICL               BIT(7) >> +#define   MAX77759_CHGR_REG_CHG_INT_CHGIN              BIT(6) >> +#define   MAX77759_CHGR_REG_CHG_INT_WCIN               BIT(5) >> +#define   MAX77759_CHGR_REG_CHG_INT_CHG                BIT(4) >> +#define   MAX77759_CHGR_REG_CHG_INT_BAT                BIT(3) >> +#define   MAX77759_CHGR_REG_CHG_INT_INLIM              BIT(2) >> +#define   MAX77759_CHGR_REG_CHG_INT_THM2               BIT(1) >> +#define   MAX77759_CHGR_REG_CHG_INT_BYP                BIT(0) >> +#define MAX77759_CHGR_REG_CHG_INT2                     0xb1 >> +#define   MAX77759_CHGR_REG_CHG_INT2_INSEL             BIT(7) >> +#define   MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1         BIT(6) >> +#define   MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2         BIT(5) >> +#define   MAX77759_CHGR_REG_CHG_INT2_BAT_OILO          BIT(4) >> +#define   MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC        BIT(3) >> +#define   MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV        BIT(2) >> +#define   MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO        BIT(1) >> +#define   MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE      BIT(0) >> +#define MAX77759_CHGR_REG_CHG_INT_MASK                 0xb2 >> +#define MAX77759_CHGR_REG_CHG_INT2_MASK                0xb3 >> +#define MAX77759_CHGR_REG_CHG_INT_OK                   0xb4 >> +#define MAX77759_CHGR_REG_CHG_DETAILS_00               0xb5 >> +#define   MAX77759_CHGR_REG_CHG_DETAILS_OO_CHGIN_DTLS  GENMASK(6, 5) >> +#define MAX77759_CHGR_REG_CHG_DETAILS_01               0xb6 >> +#define   MAX77759_CHGR_REG_CHG_DETAILS_01_BAT_DTLS    GENMASK(6, 4) >> +#define   MAX77759_CHGR_REG_CHG_DETAILS_01_CHG_DTLS    GENMASK(3, 0) >> +#define MAX77759_CHGR_REG_CHG_DETAILS_02               0xb7 >> +#define   MAX77759_CHGR_REG_CHG_DETAILS_02_CHGIN_STS   BIT(5) >> +#define MAX77759_CHGR_REG_CHG_DETAILS_03               0xb8 >> +#define MAX77759_CHGR_REG_CHG_CNFG_00                  0xb9 >> +#define   MAX77759_CHGR_REG_CHG_CNFG_00_MODE           GENMASK(3, 0) >> +#define MAX77759_CHGR_REG_CHG_CNFG_01                  0xba >> +#define MAX77759_CHGR_REG_CHG_CNFG_02                  0xbb >> +#define   MAX77759_CHGR_REG_CHG_CNFG_02_CHGCC        GENMASK(5, 0) > Small nit - there seems to be a stray TAB in this line. Will fix it in the next revision. BR, Amit > > Other than that: > Reviewed-by: André Draszik