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b=N0V0HyVSkoYv55Ireu2/X5+biQ4cUqN1Hmib4QuYSa07JZocsnnXQ3k3YOKnRMPgrzcd6bTgLMpFdaplW3NH7bbMVwZsxs8ukEpIJU0+bx8mIwoVnVX34W+O1vQXCMPRAB5u9gvxYQsaIZNPmV5kh18enwh9vyAYYZXXRPLEteU= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from PAVPR08MB9674.eurprd08.prod.outlook.com (2603:10a6:102:31d::14) by DU0PR08MB9201.eurprd08.prod.outlook.com (2603:10a6:10:415::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9818.33; Tue, 21 Apr 2026 09:58:50 +0000 Received: from PAVPR08MB9674.eurprd08.prod.outlook.com ([fe80::6f25:3681:7c97:ea2e]) by PAVPR08MB9674.eurprd08.prod.outlook.com ([fe80::6f25:3681:7c97:ea2e%4]) with mapi id 15.20.9818.032; Tue, 21 Apr 2026 09:58:50 +0000 Message-ID: Date: Tue, 21 Apr 2026 10:58:48 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 04/12] coresight: etm4x: exclude ss_status from drvdata->config To: Suzuki K Poulose , Leo Yan , Yeoreum Yun Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, james.clark@linaro.org, alexander.shishkin@linux.intel.com, jie.gan@oss.qualcomm.com References: <20260415165528.3369607-1-yeoreum.yun@arm.com> <20260415165528.3369607-5-yeoreum.yun@arm.com> <20260416155118.GM356832@e132581.arm.com> <57dbea1b-670b-4b8f-a590-1d4239bc2c76@arm.com> Content-Language: en-US From: Mike Leach In-Reply-To: <57dbea1b-670b-4b8f-a590-1d4239bc2c76@arm.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: W2U+VVxygx9T0GZ/ZCpdsLweffvUqRxZ0t0mXaA0KIfJduuoNUxdaU81b3l6fK+XbXNrosTLY7dMvuoS2QPntuJcr/qrBkgr1ynQLJZrMWPmrT6ZDs+R0WFXC1+NZt/tM7GupYV8Aw+EAColjwwRBvlR7KAPNp8/RdGqXdzpfvTlaJ3qcGkXDfRb7XXLowTMErnR/BlSgufOtcCS821TE5sDwLECh4VWVPbGghASBvWIK8S34Rp78hviNSI2sCaSd7Jawo67xRGw5ofgTt24SKL0jJe6rg6mnN+CzSb/fMg1SxgdJrmGJx7x/7+HZwI/5gG7HYtiq4+/j7CJ5piQrVbqfFgsWTSttsscrp7gvLdbS5AA7dTVjZ9+sFp/8VMKBi0IJyF9faOMq6dUrm7v4epvdPEyuBcxlWOYb0q7xF0/g1PBaWzkF9k+nWiU5zme X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2026 09:59:52.7683 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 733de7b4-8925-4cab-c8fc-08de9f8cbbd2 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AMS0EPF0000019B.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR08MB11685 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260421_030002_318251_C85C55DD X-CRM114-Status: GOOD ( 20.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, This register [bit 31] indicates if a single shot comparator has matched. So read-back provides information to the user post run to determine which if any of the comparators set in this way has actually matched. Moreover, the specification states "Software must reset this bit to 0 to re-enable single-shot control" and "Reset state is unknown. STATUS must be written to set an initial state...." Therefore this register must be written as part of any configuration so should be available in the drvdata->config for both read and write, Regards Mike On 4/21/26 09:57, Suzuki K Poulose wrote: > On 16/04/2026 16:51, Leo Yan wrote: >> On Wed, Apr 15, 2026 at 05:55:20PM +0100, Yeoreum Yun wrote: >> >> [...] >> >>> @@ -573,11 +573,9 @@ static int etm4_enable_hw(struct etmv4_drvdata >>> *drvdata) >>>           etm4x_relaxed_write32(csa, config->res_ctrl[i], >>> TRCRSCTLRn(i)); >>>       for (i = 0; i < caps->nr_ss_cmp; i++) { >>> -        /* always clear status bit on restart if using single-shot */ >>> -        if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) >>> -            config->ss_status[i] &= ~TRCSSCSRn_STATUS; >>>           etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); >>> -        etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); >>> +        /* always clear status and pending bits on restart if using >>> single-shot */ >>> +        etm4x_relaxed_write32(csa, 0x0, TRCSSCSRn(i)); >> >> In Arm ARM, D24.4.60 TRCSSCSR, bits[0..3] are RO.  I think it is >> fine for directly clear the regiser with zero (means it will only >> clear status / pending bits). >> >> [...] >> >>> @@ -1841,10 +1839,11 @@ static ssize_t sshot_status_show(struct >>> device *dev, >>>   { >>>       unsigned long val; >>>       struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); >>> +    const struct etmv4_caps *caps = &drvdata->caps; >>>       struct etmv4_config *config = &drvdata->config; >>>       raw_spin_lock(&drvdata->spinlock); >>> -    val = config->ss_status[config->ss_idx]; >>> +    val = caps->ss_cmp[config->ss_idx]; >>>       raw_spin_unlock(&drvdata->spinlock); >>>       return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); >>>   } >> >> This sysfs knob never can print out a realtime status for sshot, I am > > Won't it give the status, when the ETM was disabled (and saved back to > config), for as sysfs mode operation, where the user collects > information about the status via sysfs ? ( The question of if someone > actually makes use of this is a different question ) > > > Cheers > Suzuki > > >> fine for only printing caps->ss_cmp, this can avoid any misleading. >> >> @Suzuki, @Mike, do you agree with the change above? >> >> If maintainers agree with this, as Jie suggested, it is good to add a >> comment in the code and update the document: >> >>    Documentation/trace/coresight/coresight-etm4x-reference.rst >> >> Thanks, >> Leo >