Re: [PATCH v3 1/4] dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 07/04/2022 09:44, Vincent Whitchurch wrote:
> The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts.
> 
> The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which
> share one MCT with one global and eight local timers.  The Cortex-A53
> and Cortex-A5 do not have cache-coherency between them, and therefore
> run two separate kernels.
> 
> The Cortex-A53 boots first and starts the global free-running counter
> and also registers a clock events device using the global timer.  (This
> global timer clock events is usually replaced by arch timer clock events
> for each of the cores.)
> 
> When the A5 boots (via the A53), it should not use the global timer
> interrupts or write to the global timer registers.  This is because even
> if there are four global comparators, the control bits for all four are
> in the same registers, and we would need to synchronize between the
> cpus.  Instead, the global timer FRC (already started by the A53) should
> be used as the clock source, and one of the local timers which are not
> used by the A53 can be used for clock events on the A5.
> 
> To support this hardware, add a compatible for the MCT as well as two
> new properties to describe the hardware-mandated sharing of the FRC and
> dedicating local timers to specific processors.
> 
> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com>
> ---
> 

This is rebased on my patch:
https://lore.kernel.org/lkml/20220407194127.19004-1-krzysztof.kozlowski@linaro.org/


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

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