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[188.155.201.27]) by smtp.gmail.com with ESMTPSA id c3-20020a17090654c300b006e4e1a3e9d5sm7963714ejp.144.2022.04.08.00.16.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Apr 2022 00:16:37 -0700 (PDT) Message-ID: Date: Fri, 8 Apr 2022 09:16:37 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v3 1/4] dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT support Content-Language: en-US To: Vincent Whitchurch , tglx@linutronix.de, daniel.lezcano@linaro.org Cc: kernel@axis.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, alim.akhtar@samsung.com, devicetree@vger.kernel.org, robh+dt@kernel.org References: <20220407074432.424578-1-vincent.whitchurch@axis.com> <20220407074432.424578-2-vincent.whitchurch@axis.com> From: Krzysztof Kozlowski In-Reply-To: <20220407074432.424578-2-vincent.whitchurch@axis.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220408_001640_157494_1E56B92C X-CRM114-Status: GOOD ( 20.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 07/04/2022 09:44, Vincent Whitchurch wrote: > The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. > > The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which > share one MCT with one global and eight local timers. The Cortex-A53 > and Cortex-A5 do not have cache-coherency between them, and therefore > run two separate kernels. > > The Cortex-A53 boots first and starts the global free-running counter > and also registers a clock events device using the global timer. (This > global timer clock events is usually replaced by arch timer clock events > for each of the cores.) > > When the A5 boots (via the A53), it should not use the global timer > interrupts or write to the global timer registers. This is because even > if there are four global comparators, the control bits for all four are > in the same registers, and we would need to synchronize between the > cpus. Instead, the global timer FRC (already started by the A53) should > be used as the clock source, and one of the local timers which are not > used by the A53 can be used for clock events on the A5. > > To support this hardware, add a compatible for the MCT as well as two > new properties to describe the hardware-mandated sharing of the FRC and > dedicating local timers to specific processors. > > Signed-off-by: Vincent Whitchurch > --- > This is rebased on my patch: https://lore.kernel.org/lkml/20220407194127.19004-1-krzysztof.kozlowski@linaro.org/ Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel