Re: [PATCH 1/2] arm64: topology: Prefer PE0 on NVIDIA Olympus SMT cores

[Christian Loehle <christian.loehle@arm.com>]

On 8/31/26 19:10, Andrea Righi wrote:
> NVIDIA Olympus implements spatial SMT with symmetric steady-state PE
> capacity but two different resource modes. One-Thread Active mode gives
> one PE the full core, while waking the other PE restores Two-Thread
> Active mode and partitions decode, issue, cache, TLB, and vector
> resources. Returning to full-resource mode requires the sibling to
> remain in WFI for 10 Ki cycles.
> 
> Measurements show that pinned workloads perform equally on either PE,
> but freely migratable workloads lose substantial throughput when they
> alternate between PE identities. Consistently selecting PE0 keeps PE1
> idle, avoids repeated SMT repartitioning, and restores one-thread-per-core
> performance.
> 
> Describe this scheduling preference with SD_ASYM_PACKING and give PE0,
> identified by MPIDR_EL1.Aff0, the higher arch_asym_cpu_priority(). This is
> independent of SD_ASYM_CPUCAPACITY: SMT siblings retain equal capacity,
> while physical cores with different maximum frequencies are handled by
> a higher scheduling domain.

But why? This asympacking + CAS interaction is a bit hard to comprehend IMV.
Why can't we encode both preferences in the asym-packing priority, e.g.

priority(cpu) = is_primary(cpu) ? 2 * highest_perf(cpu)
                                : highest_perf(cpu)

so that all primary PEs are preferred over all sibling PEs, while still
preserving the highest_perf ordering within each group, and do away with
SD_ASYM_CPUCAPACITY on Vera altogether?
I had suggested this a while ago, did you have a stab at that by any chance,
too?
Am I missing something altogether?

> 
> Firmware currently provides no interface for describing the preferred
> SMT sibling. Detect Olympus by MIDR until such an interface is available.
> 
> Signed-off-by: Andrea Righi <arighi@nvidia.com>
> ---
>  arch/arm64/include/asm/topology.h |  1 +
>  arch/arm64/kernel/smp.c           |  1 +
>  arch/arm64/kernel/topology.c      | 62 +++++++++++++++++++++++++++++++
>  3 files changed, 64 insertions(+)
> > 
> diff --git a/arch/arm64/include/asm/topology.h b/arch/arm64/include/asm/topology.h
> index b9eaf4ad70850..edc1c59b3448d 100644
> --- a/arch/arm64/include/asm/topology.h
> +++ b/arch/arm64/include/asm/topology.h
> @@ -18,6 +18,7 @@ int pcibus_to_node(struct pci_bus *bus);
>  #include <linux/arch_topology.h>
>  
>  void update_freq_counters_refs(void);
> +void arm64_init_sched_topology(void);
>  
>  /* Replace task scheduler's default frequency-invariant accounting */
>  #define arch_scale_freq_tick topology_scale_freq_tick
> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
> index a61dc3016a117..0135ac4eea8bd 100644
> --- a/arch/arm64/kernel/smp.c
> +++ b/arch/arm64/kernel/smp.c
> @@ -443,6 +443,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
>  	hyp_mode_check();
>  	setup_system_features();
>  	setup_user_features();
> +	arm64_init_sched_topology();
>  	mark_linear_text_alias_ro();
>  }
>  
> diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c
> index d28438f8b83f1..0dd9eec1c4946 100644
> --- a/arch/arm64/kernel/topology.c
> +++ b/arch/arm64/kernel/topology.c
> @@ -19,6 +19,8 @@
>  #include <linux/init.h>
>  #include <linux/percpu.h>
>  #include <linux/sched/isolation.h>
> +#include <linux/sched/topology.h>
> +#include <linux/smp.h>
>  #include <linux/xarray.h>
>  
>  #include <asm/cpu.h>
> @@ -44,6 +46,66 @@
>  static DEFINE_PER_CPU_READ_MOSTLY(unsigned long, arch_max_freq_scale) =  1UL << (2 * SCHED_CAPACITY_SHIFT);
>  static cpumask_var_t amu_fie_cpus;
>  
> +/*
> + * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in
> + * two-thread active mode, with resources partitioned between the PEs.
> + *
> + * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource
> + * mode. Firmware does not currently describe this preference, so detect
> + * Olympus by MIDR until a firmware interface is available.
> + */
> +static bool olympus_prefer_pe0 __ro_after_init;
> +
> +#ifdef CONFIG_SCHED_SMT
> +static int arm64_smt_flags(void)
> +{
> +	int flags = cpu_smt_flags();
> +
> +	if (olympus_prefer_pe0)
> +		flags |= SD_ASYM_PACKING;
> +
> +	return flags;
> +}
> +#endif
> +
> +static struct sched_domain_topology_level arm64_asym_smt_topology[] = {
> +#ifdef CONFIG_SCHED_SMT
> +	SDTL_INIT(tl_smt_mask, arm64_smt_flags, SMT),
> +#endif
> +#ifdef CONFIG_SCHED_CLUSTER
> +	SDTL_INIT(tl_cls_mask, cpu_cluster_flags, CLS),
> +#endif
> +#ifdef CONFIG_SCHED_MC
> +	SDTL_INIT(tl_mc_mask, cpu_core_flags, MC),
> +#endif
> +	SDTL_INIT(tl_pkg_mask, NULL, PKG),
> +	{ NULL, },
> +};
> +
> +void __init arm64_init_sched_topology(void)
> +{
> +	if (!IS_ENABLED(CONFIG_SCHED_SMT))
> +		return;
> +
> +	if ((read_cpuid_id() & MIDR_CPU_MODEL_MASK) != MIDR_NVIDIA_OLYMPUS)
> +		return;
> +
> +	if (!topology_core_has_smt(smp_processor_id()))
> +		return;
> +
> +	olympus_prefer_pe0 = true;
> +	set_sched_topology(arm64_asym_smt_topology);
> +	pr_info("Enabling PE0 SMT preference for NVIDIA Olympus\n");
> +}
> +
> +int arch_asym_cpu_priority(int cpu)
> +{
> +	if (!olympus_prefer_pe0)
> +		return 0;
> +
> +	return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0) == 0;
> +}
> +
>  struct amu_cntr_sample {
>  	u64		arch_const_cycles_prev;
>  	u64		arch_core_cycles_prev;