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[89.77.68.124]) by smtp.gmail.com with ESMTPSA id w6sm145400ljw.89.2021.11.03.02.04.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Nov 2021 02:04:37 -0700 (PDT) Message-ID: Date: Wed, 3 Nov 2021 10:04:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.2 Subject: Re: [PATCH v2 1/2] clocksource/drivers/exynos_mct_v2: introduce Exynos MCT version 2 driver for next Exynos SoC Content-Language: en-US To: Youngmin Nam Cc: will@kernel.org, mark.rutland@arm.com, daniel.lezcano@linaro.org, tglx@linutronix.de, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, pullip.cho@samsung.com, hoony.yu@samsung.com, hajun.sung@samsung.com, myung-su.cha@samsung.com, kgene@kernel.org References: <20211102001122.27516-1-youngmin.nam@samsung.com> <20211102001122.27516-2-youngmin.nam@samsung.com> <20211102102802.GA16545@C02TD0UTHF1T.local> <20211103000945.GA48132@perf> <83f6574b-bbab-f0c3-7198-f773c3dcfc63@canonical.com> <20211103092444.GA7013@perf> From: Krzysztof Kozlowski In-Reply-To: <20211103092444.GA7013@perf> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211103_020440_583016_2D66D99A X-CRM114-Status: GOOD ( 27.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 03/11/2021 10:24, Youngmin Nam wrote: > On Wed, Nov 03, 2021 at 09:18:07AM +0100, Krzysztof Kozlowski wrote: >> On 03/11/2021 01:09, Youngmin Nam wrote: >>> On Tue, Nov 02, 2021 at 10:28:10AM +0000, Mark Rutland wrote: >>>> On Tue, Nov 02, 2021 at 09:11:21AM +0900, Youngmin Nam wrote: >>>>> Exynos MCT version 2 is composed of 1 FRC and 12 comparators. >>>>> There are no global timer and local timer anymore. >>>>> The 1 of 64bit FRC serves as "up-counter"(not "comparators"). >>>>> The 12 comaprators(not "counter") can be used as per-cpu event timer >>>>> so that it can support upto 12 cores. >>>>> And a RTC source can be used as backup clock source. >>>> >>>> [...] >>>> >>>>> +static int exynos_mct_starting_cpu(unsigned int cpu) >>>>> +{ >>>>> + struct mct_clock_event_device *mevt = per_cpu_ptr(&percpu_mct_tick, cpu); >>>>> + struct clock_event_device *evt = &mevt->evt; >>>>> + >>>>> + snprintf(mevt->name, sizeof(mevt->name), "mct_comp%d", cpu); >>>>> + >>>>> + evt->name = mevt->name; >>>>> + evt->cpumask = cpumask_of(cpu); >>>>> + evt->set_next_event = exynos_comp_set_next_event; >>>>> + evt->set_state_periodic = mct_set_state_periodic; >>>>> + evt->set_state_shutdown = mct_set_state_shutdown; >>>>> + evt->set_state_oneshot = mct_set_state_shutdown; >>>>> + evt->set_state_oneshot_stopped = mct_set_state_shutdown; >>>>> + evt->tick_resume = mct_set_state_shutdown; >>>>> + evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; >>>>> + evt->rating = 500; /* use value higher than ARM arch timer */ >>>> >>>> Previously Will asked you to try CLOCK_EVT_FEAT_PERCPU here, and to set >>>> the C3STOP flag on the arch timer via the DT when necessary, rather than >>>> trying to override the arch timer like this: >>>> >>>> https://protect2.fireeye.com/v1/url?k=72526080-2dc9598b-7253ebcf-002590f5b904-ca603717c6462908&q=1&e=be56aa83-dbac-4639-913d-d388620fe3fc&u=https%3A%2F%2Flore.kernel.org%2Fr%2F20211027073458.GA22231%40willie-the-truck >>>> >>>> There are a bunch of things that depend on the architected timer working >>>> as a clocksource (e.g. vdso, kvm), and it *should* work as a lock >>>> clockevent_device if configured correctly, and it's much more consistent >>>> with *everyone else* to use the arhcitected timer by default. >>>> >>>> Please try as Will suggested above, so that this works from day one. >>>> >>>> Thanks, >>>> Mark. >>>> >>> >>> Hi Mark. >>> It looks like you missed my previous mail. >>> https://protect2.fireeye.com/v1/url?k=ab15817a-cbf71c27-ab140a35-000babd9f1ba-123b7f313b1b1ccc&q=1&e=34c8716e-6d2e-4d8e-82fe-04777ebc5eb3&u=https%3A%2F%2Flore.kernel.org%2Fall%2F20211029035422.GA30523%40perf%2F%23t >>> >>> Yes, I believe Will's suggestion definitely will work. >>> But that is for performance not functionality. >>> As a driver for new H/W IP I would like to confirm functionality first. >>> >>> We need more time to test this feature with our exynos core power down feature. >>> And we need to do a various regression test whether there is another corner case or not. >>> So, how about we apply Will's suggetion later after the current patchset is merged first? >>> After doing our regression test with our exynos core power down feature, we can confirm this. >>> >> >> Not really, because once it is merged there is no incentive to fix it or >> simply changing it can be forgotten. Also similarly to commit >> 6282edb72bed ("clocksource/drivers/exynos_mct: Increase priority over >> ARM arch timer"), there should be a valid and serious reason to >> prioritize Exynos MCT. >> > > No, it's not. I also want to decrease MCTv2 timer rating so that we want to use arm arch timer as a default. > But this feature has to be confirmed with core power down feature enabled. > Without core power down feature, we can't comfirm this. > Ater that we need to check whether there is regression or not related power, stability, and so on. > I'm not saying I will not apply Will's suggestion but I just want to apply later after some hard test. > You repeat the same argument, the same words. Nothing new. Repeating the same won't change it, use the lower priority. This is a patch for new kernel, so there is a plenty of time to test it and it won't affect your production environment. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel