From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8545FC07C79 for ; Mon, 22 Apr 2024 12:09:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ndtYRKWaI5MyYwGeEudaZr0TLO3rv+inP6nyVA9J0L0=; b=VyhuVlxfSX0kwk FKQ9TxjgF3qYVPoh23qe+mhqHJtB3iDjvnUSCT00x475q885CtBI4Ie4/Re+FOfqcW/fCo6vOoyiW nnFpNUHGTOuxAum3+rFv0hCTNoHct71SIT/p0lgzMUYl7WwKnib6tT4vqeSSP3e+aBdCxllS67N8D GzIlgznxuNdJuLe2s8MEjmCPiirgvho/mFmZ1JkrrpUCEUtsXHSxTOEIUxIstldvCja/CAexOo/3j /AMv416F1j3GMakbsZckIVSRvvGdpGWYwTAQteDxGDROhNIghjQ3IuYqdX/YTRjt12Qdl0o9g3VAq ayPnhDeBVo6weczRpmmA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rysU5-0000000DSWU-12Nz; Mon, 22 Apr 2024 12:09:21 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rysU2-0000000DSVk-285p for linux-arm-kernel@lists.infradead.org; Mon, 22 Apr 2024 12:09:19 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 51BB4339; Mon, 22 Apr 2024 05:09:45 -0700 (PDT) Received: from [10.57.84.177] (unknown [10.57.84.177]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 551063F7BD; Mon, 22 Apr 2024 05:09:15 -0700 (PDT) Message-ID: Date: Mon, 22 Apr 2024 13:09:13 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [kvm-unit-tests PATCH 08/33] arm: realm: Make uart available before MMU is enabled Content-Language: en-GB To: Alexandru Elisei Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org, joey.gouly@arm.com, steven.price@arm.com, james.morse@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, andrew.jones@linux.dev, eric.auger@redhat.com References: <20240412103408.2706058-1-suzuki.poulose@arm.com> <20240412103408.2706058-9-suzuki.poulose@arm.com> From: Suzuki K Poulose In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240422_050918_685767_D570B127 X-CRM114-Status: GOOD ( 22.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Alexandru On 22/04/2024 12:58, Alexandru Elisei wrote: > Hi, > > On Fri, Apr 12, 2024 at 11:33:43AM +0100, Suzuki K Poulose wrote: >> From: Joey Gouly >> >> A Realm must access any emulated I/O mappings with the PTE_NS_SHARED bit set. >> This is modelled as a PTE attribute, but is actually part of the address. >> >> So, when MMU is disabled, the "physical address" must reflect this bit set. We >> access the UART early before the MMU is enabled. So, make sure the UART is >> accessed always with the bit set. >> >> Signed-off-by: Joey Gouly >> Signed-off-by: Suzuki K Poulose >> --- >> lib/arm/asm/pgtable.h | 5 +++++ >> lib/arm/io.c | 24 +++++++++++++++++++++++- >> lib/arm64/asm/pgtable.h | 5 +++++ >> 3 files changed, 33 insertions(+), 1 deletion(-) >> >> diff --git a/lib/arm/asm/pgtable.h b/lib/arm/asm/pgtable.h >> index 350039ff..7e85e7c6 100644 >> --- a/lib/arm/asm/pgtable.h >> +++ b/lib/arm/asm/pgtable.h >> @@ -112,4 +112,9 @@ static inline pte_t *pte_alloc(pmd_t *pmd, unsigned long addr) >> return pte_offset(pmd, addr); >> } >> >> +static inline unsigned long arm_shared_phys_alias(void *x) >> +{ >> + return ((unsigned long)(x) | PTE_NS_SHARED); >> +} > > Is it allowed for a realm to run in aarch32 mode? No. Realm EL1 must be Aarch64. > >> + >> #endif /* _ASMARM_PGTABLE_H_ */ >> diff --git a/lib/arm/io.c b/lib/arm/io.c >> index 836fa854..127727e4 100644 >> --- a/lib/arm/io.c >> +++ b/lib/arm/io.c >> @@ -15,6 +15,8 @@ >> #include >> #include >> #include >> +#include >> +#include >> >> #include "io.h" >> >> @@ -30,6 +32,24 @@ static struct spinlock uart_lock; >> static volatile u8 *uart0_base = UART_EARLY_BASE; >> bool is_pl011_uart; >> >> +static inline volatile u8 *get_uart_base(void) >> +{ >> + /* >> + * The address of the UART base may be different >> + * based on whether we are running with/without >> + * MMU enabled. >> + * >> + * For realms, we must force to use the shared physical >> + * alias with MMU disabled, to make sure the I/O can >> + * be emulated. >> + * When the MMU is turned ON, the mappings are created >> + * appropriately. >> + */ >> + if (mmu_enabled()) >> + return uart0_base; >> + return (u8 *)arm_shared_phys_alias((void *)uart0_base); >> +} >> + >> static void uart0_init_fdt(void) >> { >> /* >> @@ -109,9 +129,11 @@ void io_init(void) >> >> void puts(const char *s) >> { >> + volatile u8 *uart_base = get_uart_base(); >> + >> spin_lock(&uart_lock); >> while (*s) >> - writeb(*s++, uart0_base); >> + writeb(*s++, uart_base); >> spin_unlock(&uart_lock); >> } >> >> diff --git a/lib/arm64/asm/pgtable.h b/lib/arm64/asm/pgtable.h >> index 5b9f40b0..871c03e9 100644 >> --- a/lib/arm64/asm/pgtable.h >> +++ b/lib/arm64/asm/pgtable.h >> @@ -28,6 +28,11 @@ extern unsigned long prot_ns_shared; >> */ >> #define PTE_NS_SHARED (prot_ns_shared) >> >> +static inline unsigned long arm_shared_phys_alias(void *addr) >> +{ >> + return ((unsigned long)addr | PTE_NS_SHARED); >> +} > > Have you considered specifying the correct UART address at compile time using > ./configure --earlycon? Do you mean ./configure --earlycon= for Realms ? If so, there are multiple issues with that : 1. A payload could be run in a normal VM or a Realm VM. Having the above restricts using the same payload in different worlds. (e.g., comparison). 2. The IPA width of the Realm and thus the PTE_NS_SHARED is dynamic and really depends on what the VMM decides to choose the IPA size. (Could be based on user input). If any of the above fails, and a wrong earlycon address could result in "Synchronouse External Abort" into the Realm (if it is in protected IPA). Suzuki > > Thanks, > Alex >> + >> /* >> * Highest possible physical address supported. >> */ >> -- >> 2.34.1 >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel