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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6433a4b28bbsm1396845a12.28.2025.11.13.05.10.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Nov 2025 05:10:39 -0800 (PST) Message-ID: Date: Thu, 13 Nov 2025 14:10:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 10/21] drm/msm/a8xx: Add support for A8x GMU To: Akhil P Oommen , Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20251110-kaana-gpu-support-v2-0-bef18acd5e94@oss.qualcomm.com> <20251110-kaana-gpu-support-v2-10-bef18acd5e94@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251110-kaana-gpu-support-v2-10-bef18acd5e94@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEzMDA5OSBTYWx0ZWRfX1ZvCNkWf6Ff+ itT3Iq9T+bSvyFm6TpBvsEhVV9U8RP7itOEjQPhgpHNvuvwgnsoEBgNPWUi+gNL+OpBJaTKAQ8t FgiFEzeEIfeR7zaNaq+Der2rVZ+vExUZ89292iLgEewvq05J2ufpOw10Cu53JF7NWPNbbxlCrL7 1U7qNjfgPrshrcuvcwpAtmGba+CVubhxGaN5r/sN2RyYOQwTqzR3Xd9CdrOU9F8BQsnxKyj7UXf z7k4a4SUMNhfUonSzpUYQKbHLSwuxY0BCL+y3eXGbxaVzZTLRLCxuEG4up2m1+OXxScDISWi6vj 53fQMIUikXIPSY0zN/ju3YK2ZtI2IjLngbUMrqfzMAdcQE2hS8/LFFkuCoaYfkQlrmmVGB0JfTP jHzxuG4zZJbqpxS6fkrnHdDqENEB8w== X-Proofpoint-ORIG-GUID: GvaosHnnyzHDTm5Ga0XUYP5GtkPpk8Yg X-Proofpoint-GUID: GvaosHnnyzHDTm5Ga0XUYP5GtkPpk8Yg X-Authority-Analysis: v=2.4 cv=PIYCOPqC c=1 sm=1 tr=0 ts=6915d8d0 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=XMd9o5LtjS6KuIBsTZQA:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-13_02,2025-11-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511130099 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251113_051042_327017_48D57E91 X-CRM114-Status: GOOD ( 20.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/10/25 5:37 PM, Akhil P Oommen wrote: > A8x GMU configuration are very similar to A7x. Unfortunately, there are > minor shuffling in the register offsets in the GMU CX register region. > Apart from that, there is a new HFI message support to pass table like > data. This patch adds support for perf table using this new HFI > message. > > Apart from that, there is a minor rework in a6xx_gmu_rpmh_arc_votes_init() > to simplify handling of MxG to MxA fallback along with the additional > calculations for the new dependency vote. > > Signed-off-by: Akhil P Oommen > --- [...] > /* Make sure there are no outstanding RPMh votes */ > @@ -990,7 +1022,8 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) > gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, > val, (val & 1), 100, 1000); > > - if (!adreno_is_a740_family(adreno_gpu)) > + > + if (!adreno_is_a740_family(adreno_gpu) && !adreno_is_a8xx(adreno_gpu)) stray double \n above [...] > /* Check to see if we are doing a cold or warm boot */ > - if (adreno_is_a7xx(adreno_gpu)) { > + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { > status = a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) == 1 ? You skipped writing to this register above - can we count on it always being in the right state? Do we need to map VRB, or is that a topic for the future? Konrad