From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Mike Leach <mike.leach@linaro.org>, Jie Gan <jie.gan@oss.qualcomm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
James Clark <james.clark@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Mao Jinlong <quic_jinlmao@quicinc.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v3 RESEND 09/10] coresight: tmc: add read function for byte-cntr
Date: Wed, 23 Jul 2025 11:24:40 +0800 [thread overview]
Message-ID: <f7eb8a35-e17b-4324-a1a1-38a097d4b3cf@oss.qualcomm.com> (raw)
In-Reply-To: <CAJ9a7Vj_NfO7D+j11_7DbgWD-Cn9cQp4g=r9EqHMZiAU63NomQ@mail.gmail.com>
On 7/22/2025 11:01 PM, Mike Leach wrote:
> Hi,
>
> On Mon, 14 Jul 2025 at 07:32, Jie Gan <jie.gan@oss.qualcomm.com> wrote:
>>
>> The byte-cntr read function always reads trace data from the deactivated
>> and filled buffer which is already synced. The read function will fail
>> when the ETR cannot find a available buffer to receive trace data.
>>
>> The read function terminates when the path is disabled or interrupted by a
>> signal.
>>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> .../hwtracing/coresight/coresight-tmc-core.c | 31 ++++++-
>> .../hwtracing/coresight/coresight-tmc-etr.c | 90 +++++++++++++++++++
>> drivers/hwtracing/coresight/coresight-tmc.h | 3 +
>> 3 files changed, 120 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
>> index 354faeeddbb2..3ab25adc4e4d 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
>> @@ -318,14 +318,18 @@ static int tmc_open(struct inode *inode, struct file *file)
>> return 0;
>> }
>>
>> -static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len,
>> - char **bufpp)
>> +static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
>> + struct ctcu_byte_cntr *byte_cntr_data,
>> + loff_t pos, size_t len, char **bufpp)
>
> Don't change "core" functionalilty to add in bytecntr parameters.
>
> Use helper functions to have a pattern such as:
>
> if (bytecntr_active())
> call_byte_cntr_fn()
> else
> call_standard_fn()
got it. Will fix in next version.
Thanks,
Jie
>
>> {
>> switch (drvdata->config_type) {
>> case TMC_CONFIG_TYPE_ETB:
>> case TMC_CONFIG_TYPE_ETF:
>> return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp);
>> case TMC_CONFIG_TYPE_ETR:
>> + if (byte_cntr_data && byte_cntr_data->thresh_val)
>> + return tmc_byte_cntr_get_data(drvdata, byte_cntr_data, len, bufpp);
>> +
>> return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
>> }
>>
>> @@ -339,7 +343,21 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
>> ssize_t actual;
>> struct tmc_drvdata *drvdata = container_of(file->private_data,
>> struct tmc_drvdata, miscdev);
>> - actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
>> + struct coresight_device *helper = coresight_get_helper(drvdata->csdev,
>> + CORESIGHT_DEV_SUBTYPE_HELPER_CTCU);
>> + struct ctcu_byte_cntr *byte_cntr_data = NULL;
>> + struct ctcu_drvdata *ctcu_drvdata = NULL;
>> + int port;
>> +
>> + if (helper) {
>> + port = coresight_get_port_helper(drvdata->csdev, helper);
>> + if (port >= 0) {
>> + ctcu_drvdata = dev_get_drvdata(helper->dev.parent);
>> + byte_cntr_data = &ctcu_drvdata->byte_cntr_data[port];
>> + }
>> + }
>> +
>> + actual = tmc_get_sysfs_trace(drvdata, byte_cntr_data, *ppos, len, &bufp);
>> if (actual <= 0)
>> return 0;
>>
>> @@ -349,7 +367,12 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
>> return -EFAULT;
>> }
>>
>> - *ppos += actual;
>> + if (byte_cntr_data && byte_cntr_data->thresh_val) {
>> + byte_cntr_data->total_size += actual;
>> + drvdata->reading_node->pos += actual;
>> + } else
>> + *ppos += actual;
>> +
>> dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual);
>>
>> return actual;
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
>> index 3e3e1b5e78ca..174411e76047 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
>> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
>> @@ -1163,6 +1163,10 @@ ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
>> ssize_t actual = len;
>> struct etr_buf *etr_buf = drvdata->sysfs_buf;
>>
>> + /* Reading the buffer from the buf_node if it exists*/
>> + if (drvdata->reading_node)
>> + etr_buf = drvdata->reading_node->sysfs_buf;
>> +
>> if (pos + actual > etr_buf->len)
>> actual = etr_buf->len - pos;
>> if (actual <= 0)
>> @@ -1339,6 +1343,92 @@ static bool tmc_byte_cntr_switch_buffer(struct tmc_drvdata *drvdata,
>> return found_free_buf;
>> }
>>
>> +/*
>> + * tmc_byte_cntr_get_data() - reads data from the deactivated and filled buffer.
>> + * The byte-cntr reading work reads data from the deactivated and filled buffer.
>> + * The read operation waits for a buffer to become available, either filled or
>> + * upon timeout, and then reads trace data from the synced buffer.
>> + */
>
> This entire function should be moved to one of the byte-cntr source files.
>
>> +ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata,
>> + struct ctcu_byte_cntr *byte_cntr_data,
>> + size_t len, char **bufpp)
>> +{
>> + size_t thresh_val = byte_cntr_data->thresh_val;
>> + atomic_t *irq_cnt = &byte_cntr_data->irq_cnt;
>> + struct etr_buf *sysfs_buf = drvdata->sysfs_buf;
>> + struct device *dev = &drvdata->csdev->dev;
>> + struct etr_buf_node *nd, *next;
>> + ssize_t size = sysfs_buf->size;
>> + ssize_t actual;
>> + loff_t pos;
>> + int ret;
>> +
>> +wait_buffer:
>> + if (!byte_cntr_data->reading_buf) {
>> + ret = wait_event_interruptible_timeout(byte_cntr_data->wq,
>> + ((atomic_read(irq_cnt) + 1) * thresh_val >= size) ||
>> + !byte_cntr_data->enable,
>> + BYTE_CNTR_TIMEOUT);
>> + if (ret < 0)
>> + return ret;
>> + /*
>> + * The current etr_buf is almost full or timeout is triggered,
>> + * so switch the buffer and mark the switched buffer as reading.
>> + */
>> + if (byte_cntr_data->enable) {
>> + if (!tmc_byte_cntr_switch_buffer(drvdata, byte_cntr_data)) {
>> + dev_err(dev, "Switch buffer failed for byte-cntr\n");
>> + return -EINVAL;
>> + }
>> +
>> + byte_cntr_data->reading_buf = true;
>> + } else {
>> + if (!drvdata->reading_node) {
>> + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, node) {
>> + if (nd->sysfs_buf == sysfs_buf) {
>> + nd->pos = 0;
>> + drvdata->reading_node = nd;
>> + break;
>> + }
>> + }
>> + }
>> +
>> + pos = drvdata->reading_node->pos;
>> + actual = tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
>> + if (actual > 0)
>> + return actual;
>> +
>> + drvdata->reading_node = NULL;
>> +
>> + /* Exit byte-cntr reading */
>> + return -EINVAL;
>> + }
>> + }
>> +
>> + /* Check the status of current etr_buf*/
>> + if ((atomic_read(irq_cnt) + 1) * thresh_val >= size)
>> + /*
>> + * Unlikely to find a free buffer to switch, so just disable
>> + * the ETR for a while.
>> + */
>> + if (!tmc_byte_cntr_switch_buffer(drvdata, byte_cntr_data))
>> + dev_info(dev, "No available buffer to store data, disable ETR\n");
>> +
>> + pos = drvdata->reading_node->pos;
>> + actual = tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp);
>> + if (actual == 0) {
>> + /* Reading work for marked buffer has finished, reset flags */
>> + drvdata->reading_node->reading = false;
>> + byte_cntr_data->reading_buf = false;
>> + drvdata->reading_node = NULL;
>> +
>> + /* Nothing in the buffer, wait for next buffer to be filled */
>> + goto wait_buffer;
>> + }
>> +
>> + return actual;
>> +}
>> +
>> static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
>> {
>> int ret = 0;
>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
>> index 1dbba0bc50a3..4136ec5ecaf7 100644
>> --- a/drivers/hwtracing/coresight/coresight-tmc.h
>> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
>> @@ -364,6 +364,9 @@ int tmc_read_prepare_byte_cntr(struct tmc_drvdata *drvdata,
>> struct ctcu_byte_cntr *byte_cntr_data);
>> int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *drvdata,
>> struct ctcu_byte_cntr *byte_cntr_data);
>
> Declare this in a byte_cntr header file, not here.
I will add it to,for example, ctcu_byte_cntr_read_ops->read.
So I think I dont need define it in any header file in future.
Will remove it.
Thanks,
Jie
>
>> +ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata,
>> + struct ctcu_byte_cntr *byte_cntr_data,
>> + size_t len, char **bufpp);
>>
>> #define TMC_REG_PAIR(name, lo_off, hi_off) \
>> static inline u64 \
>> --
>> 2.34.1
>>
>
>
next prev parent reply other threads:[~2025-07-23 3:27 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-14 6:30 [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 01/10] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-07-16 10:20 ` Mike Leach
2025-07-17 0:55 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 02/10] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-07-18 8:37 ` Mike Leach
2025-07-18 9:36 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 03/10] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-07-22 15:23 ` Mike Leach
2025-07-23 1:15 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 05/10] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 06/10] coresight: tmc: add create/delete functions for etr_buf_node Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 07/10] coresight: tmc: add prepare/unprepare functions for byte-cntr Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 08/10] coresight: tmc: add a switch buffer function " Jie Gan
2025-07-22 14:09 ` Mike Leach
2025-07-23 3:29 ` Jie Gan
2025-07-23 5:10 ` Jie Gan
2025-07-14 6:31 ` [PATCH v3 RESEND 09/10] coresight: tmc: add read " Jie Gan
2025-07-22 15:01 ` Mike Leach
2025-07-23 3:24 ` Jie Gan [this message]
2025-07-14 6:31 ` [PATCH v3 RESEND 10/10] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Jie Gan
2025-07-22 15:09 ` [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR Mike Leach
2025-07-23 1:26 ` Jie Gan
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