Re: [PATCH] ARM: mm: skip cleaning of idmap page tables on LPAE capable cores

From: Marc Zyngier <marc.zyngier@arm.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>,
	Russell King <linux@armlinux.org.uk>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] ARM: mm: skip cleaning of idmap page tables on LPAE capable cores
Date: Thu, 13 Dec 2018 11:40:18 +0000	[thread overview]
Message-ID: <f7ede136-2b1e-9758-b82c-7d645c9c7dda@arm.com> (raw)
In-Reply-To: <CAKv+Gu-x7G8_Zndn8H=PB7WOx1fFhpCHTsANkkoATFjozJh8wA@mail.gmail.com>

On 13/12/2018 10:57, Ard Biesheuvel wrote:
> On Mon, 10 Dec 2018 at 17:13, Marc Zyngier <marc.zyngier@arm.com> wrote:
>>
>> On 10/12/2018 15:48, Russell King - ARM Linux wrote:
>>> On Mon, Dec 10, 2018 at 04:28:55PM +0100, Ard Biesheuvel wrote:
>>>> Since only LPAE capable CPUs may execute under virtualization, and
>>>> considering that LPAE capable CPUs are guaranteed to have cache
>>>> coherent page table walkers (per the architecture), let's only
>>>> perform this cache maintenance on non-LPAE cores.
>>>
>>> That statement doesn't stack up.  What about Cortex A15, which is a
>>> 32-bit core with LPAE support?  TI Keystone2 SoCs fall into this
>>> category.
>>
>> As already documented in dcadda146f4fd25a732382747f306465d337cda6
>> ("arm/kvm: excise redundant cache maintenance"):
>>
>> <quote>
>> Per ARM DDI 0406C.c, section B1.7 ("The Virtualization Extensions"), the
>> virtualization extensions mandate the multiprocessing extensions.
>>
>> Per ARM DDI 0406C.c, section B3.10.1 ("General TLB maintenance
>> requirements"), as described in the sub-section titled "TLB maintenance
>> operations and the memory order model", this maintenance is not required
>> in the presence of the multiprocessing extensions.
>> </quote>
>>
>> Furthermore, as per B1.6 ("The Large Physical Address Extension") from
>> the same document:
>>
>> <quote>
>> An implementation that includes the Large Physical Address Extension
>> must implement the Multiprocessing Extensions and therefore cannot
>> include the FCSE, see Use of the Fast Context Switch Extension on page
>> AppxI-2475.
>> </quote>
>>
>> So on a core like Cortex A15 where we have both MP, VE and LPAE, we
>> should be able to assume a coherent page table walker.
>>
> 
> Thanks Marc
> 
> I'll drop this into the patch system.

Cool, it'd be useful to have this from an architecture compliance point
of view.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel