From: Frank Binns <Frank.Binns@imgtec.com>
To: "tzimmermann@suse.de" <tzimmermann@suse.de>,
"simona@ffwll.ch" <simona@ffwll.ch>,
Matt Coster <Matt.Coster@imgtec.com>,
"kristo@kernel.org" <kristo@kernel.org>,
"robh@kernel.org" <robh@kernel.org>,
"airlied@gmail.com" <airlied@gmail.com>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"nm@ti.com" <nm@ti.com>,
"maarten.lankhorst@linux.intel.com"
<maarten.lankhorst@linux.intel.com>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"mripard@kernel.org" <mripard@kernel.org>,
"vigneshr@ti.com" <vigneshr@ti.com>
Cc: "detheridge@ti.com" <detheridge@ti.com>, "rs@ti.com" <rs@ti.com>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Alessio Belle <Alessio.Belle@imgtec.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"m.wilczynski@samsung.com" <m.wilczynski@samsung.com>,
Alexandru Dadu <Alexandru.Dadu@imgtec.com>
Subject: Re: [PATCH v5 03/18] drm/imagination: Update register defs for newer GPUs
Date: Tue, 1 Apr 2025 13:40:43 +0000 [thread overview]
Message-ID: <f8a0769425365e6e0e0e7bb547cc1347ebbf872d.camel@imgtec.com> (raw)
In-Reply-To: <20250326-sets-bxs-4-64-patch-v1-v5-3-e4c46e8280a9@imgtec.com>
On Wed, 2025-03-26 at 16:48 +0000, Matt Coster wrote:
> From: Alessio Belle <alessio.belle@imgtec.com>
>
> Update the register define header to a newer version that covers more
> recent GPUs, including BXS-4-64.
>
> Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
> Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Patches 3-16 are:
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Thanks
Frank
> ---
> Changes in v5:
> - None
> - Link to v4: https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-3-d987cf4ca439@imgtec.com
> Changes in v4:
> - None
> - Link to v3: https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-3-143b3dbef02f@imgtec.com
> Changes in v3:
> - Added
> ---
> drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h | 153 +++++++++++++++++++++---
> 1 file changed, 134 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
> index 2a90d02796d3e071b18e18dead105e29798bcddc..790c97f80a2ac03ac76b933d009a2f9cfc6003f7 100644
> --- a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
> +++ b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
> @@ -827,6 +827,120 @@
> #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU
> #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_EN 0x00000001U
>
> +/* Register ROGUE_CR_EVENT_CLEAR */
> +#define ROGUE_CR_EVENT_CLEAR 0x0138U
> +#define ROGUE_CR_EVENT_CLEAR__ROGUEXE__MASKFULL 0x00000000E01DFFFFULL
> +#define ROGUE_CR_EVENT_CLEAR__SIGNALS__MASKFULL 0x00000000E007FFFFULL
> +#define ROGUE_CR_EVENT_CLEAR_MASKFULL 0x00000000FFFFFFFFULL
> +#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_SHIFT 31U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_CLRMSK 0x7FFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_TDM_FENCE_FINISHED_EN 0x80000000U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_SHIFT 30U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_CLRMSK 0xBFFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_TDM_BUFFER_STALL_EN 0x40000000U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_SHIFT 29U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_CLRMSK 0xDFFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_SIGNAL_FAILURE_EN 0x20000000U
> +#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_SHIFT 28U
> +#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_CLRMSK 0xEFFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_DPX_OUT_OF_MEMORY_EN 0x10000000U
> +#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_SHIFT 27U
> +#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_CLRMSK 0xF7FFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_DPX_MMU_PAGE_FAULT_EN 0x08000000U
> +#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_SHIFT 26U
> +#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_CLRMSK 0xFBFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RPM_OUT_OF_MEMORY_EN 0x04000000U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_SHIFT 25U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_CLRMSK 0xFDFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC3_FINISHED_EN 0x02000000U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_SHIFT 24U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_CLRMSK 0xFEFFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC2_FINISHED_EN 0x01000000U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_SHIFT 23U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_CLRMSK 0xFF7FFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC1_FINISHED_EN 0x00800000U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_SHIFT 22U
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_CLRMSK 0xFFBFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_FBA_FC0_FINISHED_EN 0x00400000U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_SHIFT 21U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_CLRMSK 0xFFDFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC3_FINISHED_EN 0x00200000U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_SHIFT 20U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_CLRMSK 0xFFEFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC2_FINISHED_EN 0x00100000U
> +#define ROGUE_CR_EVENT_CLEAR_SAFETY_SHIFT 20U
> +#define ROGUE_CR_EVENT_CLEAR_SAFETY_CLRMSK 0xFFEFFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_SAFETY_EN 0x00100000U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_SHIFT 19U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_CLRMSK 0xFFF7FFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC1_FINISHED_EN 0x00080000U
> +#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_SHIFT 19U
> +#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_CLRMSK 0xFFF7FFFFU
> +#define ROGUE_CR_EVENT_CLEAR_SLAVE_REQ_EN 0x00080000U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_SHIFT 18U
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_CLRMSK 0xFFFBFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_RDM_FC0_FINISHED_EN 0x00040000U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U
> +#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_CLRMSK 0xFFFBFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_TDM_CONTEXT_STORE_FINISHED_EN 0x00040000U
> +#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_SHIFT 17U
> +#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_CLRMSK 0xFFFDFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_SHG_FINISHED_EN 0x00020000U
> +#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_SHIFT 17U
> +#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_CLRMSK 0xFFFDFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_SPFILTER_SIGNAL_UPDATE_EN 0x00020000U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_SHIFT 16U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_CLRMSK 0xFFFEFFFFU
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_BUFFER_STALL_EN 0x00010000U
> +#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_SHIFT 15U
> +#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_CLRMSK 0xFFFF7FFFU
> +#define ROGUE_CR_EVENT_CLEAR_USC_TRIGGER_EN 0x00008000U
> +#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_SHIFT 14U
> +#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_CLRMSK 0xFFFFBFFFU
> +#define ROGUE_CR_EVENT_CLEAR_ZLS_FINISHED_EN 0x00004000U
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_SHIFT 13U
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_CLRMSK 0xFFFFDFFFU
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_ACK_EN 0x00002000U
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_SHIFT 12U
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_CLRMSK 0xFFFFEFFFU
> +#define ROGUE_CR_EVENT_CLEAR_GPIO_REQ_EN 0x00001000U
> +#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_SHIFT 11U
> +#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_CLRMSK 0xFFFFF7FFU
> +#define ROGUE_CR_EVENT_CLEAR_POWER_ABORT_EN 0x00000800U
> +#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_SHIFT 10U
> +#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_CLRMSK 0xFFFFFBFFU
> +#define ROGUE_CR_EVENT_CLEAR_POWER_COMPLETE_EN 0x00000400U
> +#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_SHIFT 9U
> +#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_CLRMSK 0xFFFFFDFFU
> +#define ROGUE_CR_EVENT_CLEAR_MMU_PAGE_FAULT_EN 0x00000200U
> +#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_SHIFT 8U
> +#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_CLRMSK 0xFFFFFEFFU
> +#define ROGUE_CR_EVENT_CLEAR_PM_3D_MEM_FREE_EN 0x00000100U
> +#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_SHIFT 7U
> +#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_CLRMSK 0xFFFFFF7FU
> +#define ROGUE_CR_EVENT_CLEAR_PM_OUT_OF_MEMORY_EN 0x00000080U
> +#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_SHIFT 6U
> +#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_CLRMSK 0xFFFFFFBFU
> +#define ROGUE_CR_EVENT_CLEAR_TA_TERMINATE_EN 0x00000040U
> +#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_SHIFT 5U
> +#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_CLRMSK 0xFFFFFFDFU
> +#define ROGUE_CR_EVENT_CLEAR_TA_FINISHED_EN 0x00000020U
> +#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_SHIFT 4U
> +#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_CLRMSK 0xFFFFFFEFU
> +#define ROGUE_CR_EVENT_CLEAR_ISP_END_MACROTILE_EN 0x00000010U
> +#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_SHIFT 3U
> +#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_CLRMSK 0xFFFFFFF7U
> +#define ROGUE_CR_EVENT_CLEAR_PIXELBE_END_RENDER_EN 0x00000008U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_SHIFT 2U
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_CLRMSK 0xFFFFFFFBU
> +#define ROGUE_CR_EVENT_CLEAR_COMPUTE_FINISHED_EN 0x00000004U
> +#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_SHIFT 1U
> +#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_CLRMSK 0xFFFFFFFDU
> +#define ROGUE_CR_EVENT_CLEAR_KERNEL_FINISHED_EN 0x00000002U
> +#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_SHIFT 0U
> +#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU
> +#define ROGUE_CR_EVENT_CLEAR_TLA_COMPLETE_EN 0x00000001U
> +
> /* Register ROGUE_CR_TIMER */
> #define ROGUE_CR_TIMER 0x0160U
> #define ROGUE_CR_TIMER_MASKFULL 0x8000FFFFFFFFFFFFULL
> @@ -6031,25 +6145,6 @@
> #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U
> #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U
>
> -/* Register ROGUE_CR_ECC_RAM_ERR_INJ */
> -#define ROGUE_CR_ECC_RAM_ERR_INJ 0xF340U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_MASKFULL 0x000000000000001FULL
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_EN 0x00000010U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_CLRMSK 0xFFFFFFF7U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_USC_EN 0x00000008U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN 0x00000004U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_CLRMSK 0xFFFFFFFDU
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_EN 0x00000002U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_CLRMSK 0xFFFFFFFEU
> -#define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_EN 0x00000001U
> -
> /* Register ROGUE_CR_ECC_RAM_INIT_KICK */
> #define ROGUE_CR_ECC_RAM_INIT_KICK 0xF348U
> #define ROGUE_CR_ECC_RAM_INIT_KICK_MASKFULL 0x000000000000001FULL
> @@ -6163,6 +6258,26 @@
> #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU
> #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U
>
> +/* Register ROGUE_CR_FAULT_FW_STATUS */
> +#define ROGUE_CR_FAULT_FW_STATUS 0xF3B0U
> +#define ROGUE_CR_FAULT_FW_STATUS_MASKFULL 0x0000000000010001ULL
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_SHIFT 16U
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_CLRMSK 0xFFFEFFFFU
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_CORRECT_EN 0x00010000U
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_SHIFT 0U
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_CLRMSK 0xFFFFFFFEU
> +#define ROGUE_CR_FAULT_FW_STATUS_CPU_DETECT_EN 0x00000001U
> +
> +/* Register ROGUE_CR_FAULT_FW_CLEAR */
> +#define ROGUE_CR_FAULT_FW_CLEAR 0xF3B8U
> +#define ROGUE_CR_FAULT_FW_CLEAR_MASKFULL 0x0000000000010001ULL
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_SHIFT 16U
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_CLRMSK 0xFFFEFFFFU
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_CORRECT_EN 0x00010000U
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_SHIFT 0U
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_CLRMSK 0xFFFFFFFEU
> +#define ROGUE_CR_FAULT_FW_CLEAR_CPU_DETECT_EN 0x00000001U
> +
> /* Register ROGUE_CR_MTS_SAFETY_EVENT_ENABLE */
> #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE 0xF3D8U
> #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL
>
next prev parent reply other threads:[~2025-04-01 13:43 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-26 16:48 [PATCH v5 00/18] Imagination BXS-4-64 MC1 GPU support Matt Coster
2025-03-26 16:48 ` [PATCH v5 01/18] dt-bindings: gpu: img: Future-proofing enhancements Matt Coster
2025-03-27 7:55 ` Krzysztof Kozlowski
2025-04-01 16:45 ` Michal Wilczynski
2025-04-14 9:25 ` Matt Coster
2025-03-26 16:48 ` [PATCH v5 02/18] dt-bindings: gpu: img: Add BXS-4-64 devicetree bindings Matt Coster
2025-03-27 7:56 ` Krzysztof Kozlowski
2025-03-26 16:48 ` [PATCH v5 03/18] drm/imagination: Update register defs for newer GPUs Matt Coster
2025-04-01 13:40 ` Frank Binns [this message]
2025-03-26 16:48 ` [PATCH v5 04/18] drm/imagination: Use new generic compatible string Matt Coster
2025-03-26 16:48 ` [PATCH v5 05/18] drm/imagination: Add power domain control Matt Coster
2025-03-26 16:48 ` [PATCH v5 06/18] drm/imagination: Mask GPU IRQs in threaded handler Matt Coster
2025-03-26 16:48 ` [PATCH v5 07/18] drm/imagination: Handle Rogue safety event IRQs Matt Coster
2025-03-26 16:48 ` [PATCH v5 08/18] drm/imagination: Remove firmware enable_reg Matt Coster
2025-03-26 16:48 ` [PATCH v5 09/18] drm/imagination: Rename event_mask -> status_mask Matt Coster
2025-03-26 16:48 ` [PATCH v5 10/18] drm/imagination: Make has_fixed_data_addr a value Matt Coster
2025-03-26 16:48 ` [PATCH v5 11/18] drm/imagination: Use a lookup table for fw defs Matt Coster
2025-03-26 16:48 ` [PATCH v5 12/18] drm/imagination: Use callbacks for fw irq handling Matt Coster
2025-03-26 16:48 ` [PATCH v5 13/18] drm/imagination: Move ELF fw utils to common file Matt Coster
2025-03-26 16:48 ` [PATCH v5 14/18] drm/imagination: Add RISC-V firmware processor support Matt Coster
2025-03-26 16:48 ` [PATCH v5 15/18] drm/imagination: Use cached memory with dma_coherent Matt Coster
2025-03-26 16:48 ` [PATCH v5 16/18] drm/imagination: Add support for TI AM68 GPU Matt Coster
2025-03-26 16:48 ` [PATCH DO NOT MERGE v5 17/18] arm64: dts: ti: k3-am62: New GPU binding details Matt Coster
2025-03-26 16:48 ` [PATCH DO NOT MERGE v5 18/18] arm64: dts: ti: k3-j721s2: Add GPU node Matt Coster
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f8a0769425365e6e0e0e7bb547cc1347ebbf872d.camel@imgtec.com \
--to=frank.binns@imgtec.com \
--cc=Alessio.Belle@imgtec.com \
--cc=Alexandru.Dadu@imgtec.com \
--cc=Matt.Coster@imgtec.com \
--cc=airlied@gmail.com \
--cc=conor+dt@kernel.org \
--cc=detheridge@ti.com \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=kristo@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=m.wilczynski@samsung.com \
--cc=maarten.lankhorst@linux.intel.com \
--cc=mripard@kernel.org \
--cc=nm@ti.com \
--cc=robh@kernel.org \
--cc=rs@ti.com \
--cc=simona@ffwll.ch \
--cc=tzimmermann@suse.de \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox