From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46683CA0ECA for ; Tue, 12 Sep 2023 10:45:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Content-ID:In-Reply-To: References:Message-ID:Date:Subject:CC:To:From:Reply-To:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qa/Jeciu+/M1mLYy/zw/BKrfO6g8Z6sCdvB8voAvSP4=; b=ielCVQCNF6ht6a XKFLokwkKp3oLAXsywfm2/QaUkl9kP+kAXN4Su6fb8z4KfG+P3IJzVkBwD8JoR9redv82n/2gc33q VytVpVY/OINNDVE3dyeFbcdQKv3houczr7tX2MvAGmD+/iKUaA3iIZLnDt0gm17y2/ZFtPOkON4x5 jAelOt76WB4Dn6uC08vF2Lg/QdICQ6S+w5luf5PKCN97eVNvYEqrLcP/hdxozYfOjEFNbInfZpq6a lHHmk+dGux8tq6JuhAVvMvF3Y47riPPK07UEGEYMf1kTua+SVNzkgC884BCzubFTZFmLIOOjnOgEg e4QRWi573o0kaBGz8FVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qg0sy-002zIk-2b; Tue, 12 Sep 2023 10:44:48 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qg0su-002zFg-0H for linux-arm-kernel@lists.infradead.org; Tue, 12 Sep 2023 10:44:47 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1694515484; x=1726051484; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-id:content-transfer-encoding: mime-version; bh=Cst6JOKQRYhZueYtZvQs8ds4ozKbBZ9sMLULiVD8wZM=; b=T051ecQDJQdmNh7Lv3CVJ4emprfSbW/BPo7W71rXhiHPEywVf0mj7Ryk vpLk2YO3NGqYfompSKG6h3Q1ClHH6Pr9LkMVAf4QcUlSR28htS/ogmskx bBSY+3xSCuwkOykDfw22WXvjkdY7z6oAbr6btmgXsXDTbV1HHtbo1jWIO aVag3Ofb7CBkitNb5NLhnFY6B0PtH/WL29X/EhFbGWm41ItlXbqfY8wGl mzUYrzHHj75X6erTZCv9vprfBossj6h05Y00kETAwy/nYikHrXMZWXA2X r31EKB1SDccelfpwD3PNaP9C6Skkq750eGtqeZz1pu9Q5tADAv+IEeUXv g==; X-CSE-ConnectionGUID: TiaSJnz2QZScr7UPF8L4rA== X-CSE-MsgGUID: vrO6X55HQFqXjO3WZkGRmw== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.02,139,1688454000"; d="scan'208";a="4069903" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 12 Sep 2023 03:44:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 12 Sep 2023 03:44:28 -0700 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21 via Frontend Transport; Tue, 12 Sep 2023 03:44:28 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=X5BzhVkzs1+63fP47Lstydh9atomRjX1qLgREvAH8f58hW9HhKkgwR7dfOTG7iXC+h0E7Nz2fYm9yHvBU0mSYMFwF6MBck9IejTV34bVAt9ficFPo9sKNBQa4TmbGnUJbkL2JDyUepbPhhIic9NEs8TtaJxrgpqhYBTjAfA3zyZuCa7G/sz1Qdikj2R1G/qK6RYmtrku4lXYXg5+JEvBqR2cYjommn87GHOPTx4HEabVunkVcA/fsL97i4kQ0MMH8bwxMGRcMc2afstTHQvIUxZ0Z2uv0XK9bID8g7kcdAat1VLdSHb+NM+/SI343efi8bu1bdO2h4nwQ4ajDmAo2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Cst6JOKQRYhZueYtZvQs8ds4ozKbBZ9sMLULiVD8wZM=; b=kEGCuqRMbgLsvyLjOJ4wwZaecuSmjYtUUPnLPpoM6evCJc7QouR+LdhnFCykgWqLrQcuqKG1slodpdDeUtcg5rwdaB9Oc95Ngmx2uMuwCY1ZgWm0xujsUyhNirS0e+qHUVd4spe8P8eUNPBlCbCzE5VOxG5GqkDsfIwB2/1P2KSoV/4iDludGHcj4gUyArEtDuZCuDL+iiRgGfpojyV6BxInKmy6w69AXBsO9VF4HehBiCav7zfCgwXWCz4mQBJlqsPWiXJZmcvQq2qg9ylQs+K7gQChE1NHi0WYVq6RiUlfbyKgPHoOzBRP9+g5H1BDhBsLzqfe0WMok67vwb8KNQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=microchip.com; dmarc=pass action=none header.from=microchip.com; dkim=pass header.d=microchip.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector2-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Cst6JOKQRYhZueYtZvQs8ds4ozKbBZ9sMLULiVD8wZM=; b=XAmOSqBsrPDf2jfp/s5oPhYykj7P28zw9tjImI16TP6RyvCfxGlLmKNV+AOz7o83/46lhiU8eBsd4lz09A5Xu/ERnTW8wkEGRGUIeaU37YiXss2CJpUIRevq1pQxKubblnnKgFRt7zmzrOTXdQEN4X+4KG5n7pEkM6i41xlmnz4= Received: from IA1PR11MB6193.namprd11.prod.outlook.com (2603:10b6:208:3eb::19) by CO1PR11MB5057.namprd11.prod.outlook.com (2603:10b6:303:6c::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6768.37; Tue, 12 Sep 2023 10:44:25 +0000 Received: from IA1PR11MB6193.namprd11.prod.outlook.com ([fe80::8bf2:b185:cfb9:de89]) by IA1PR11MB6193.namprd11.prod.outlook.com ([fe80::8bf2:b185:cfb9:de89%5]) with mapi id 15.20.6768.029; Tue, 12 Sep 2023 10:44:25 +0000 From: To: , , , , , , , , , , CC: , , , , , , Subject: Re: [PATCH v4 5/8] drm: atmel_hlcdc: Add support for XLCDC in atmel LCD driver Thread-Topic: [PATCH v4 5/8] drm: atmel_hlcdc: Add support for XLCDC in atmel LCD driver Thread-Index: AQHZ11OCc5aAf05oHUOQCl37yNHQKLASxGkAgARZH4A= Date: Tue, 12 Sep 2023 10:44:25 +0000 Message-ID: References: <20230825125444.93222-1-manikandan.m@microchip.com> <20230825125444.93222-6-manikandan.m@microchip.com> <1a3154b5-e849-dc60-8434-892b38cec87e@tuxon.dev> In-Reply-To: <1a3154b5-e849-dc60-8434-892b38cec87e@tuxon.dev> Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microchip.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: IA1PR11MB6193:EE_|CO1PR11MB5057:EE_ x-ms-office365-filtering-correlation-id: b12ef4b2-d7cf-49da-fd0d-08dbb37d3b61 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: HOY6mHSmOe/qJClWVok1EOg4MxN+4nW11xHtB8uM8Cz35Ac43oPbzLfhTPIbIgidN1o+zw4rkKV/5JLL3c+4LQ4M03TGEmS6bjTHbGaWlnF26kaVyKKWepcwFkI/gXe7GLTAJ4quxwlhyvf0QyqrBQMHFmIjkvBtPU6cStwf27tlSZzJV3rJt6ThS63ba0281HCoe38tm5iCRxlBcg3hGwJmQUZQ0VlDlywnwsFWZYpQTeI5AO3WFTH3O9tvch2bvblDy1JAhITQbHcmMmLHX1LvEetPCoIPo6xRsYV12CpVuK+uLGORMRP8R8C/WyY1vM9KUIRlNduZpk1Y/sJezGlRqK2GVU6fJKRKiasbbgVgtUZL8TPSPV3B10OO4bHZAFAHM11o3Sj9d83KxuFVa7WW5fxxROXXidB5bx8xqg/wRiHFegKJQd8OCiMUnMFQWbDOTk4wRc+SUf3AQWa/MdzI+nzDFelSiYShEnafaJMJjSgqtglFKlyn2sWE+R2KNQ8lol8Q6Lw3q+UEkGof3u7BVG4XIskKYJ6x9SoMKfsXOnsABikpEBM5oDiQiUle1/4Jm5tSplBn+iKn4Xt/I765btYovWUb7zfoEvwwhcp4zs3QPnyFEP3xXo3ibh3Vqizbj2+1p0+pn/wJ0dz/IgdbVvfxm1s9+aH8+JUdUSJJ520+0cS1EUbnp4mdyRr6 x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:IA1PR11MB6193.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(366004)(396003)(376002)(39860400002)(346002)(136003)(186009)(1800799009)(451199024)(66946007)(83380400001)(71200400001)(107886003)(478600001)(6512007)(53546011)(6486002)(6506007)(36756003)(31696002)(31686004)(2616005)(122000001)(66446008)(921005)(86362001)(26005)(38070700005)(38100700002)(66476007)(66556008)(54906003)(76116006)(64756008)(91956017)(110136005)(316002)(966005)(30864003)(7416002)(2906002)(41300700001)(5660300002)(8676002)(8936002)(4326008)(21314003)(45980500001)(579004)(559001);DIR:OUT;SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?B?WkRqdGtYU3dDODlJT0t2aFEzd0IzM3RaamtCbVpCeTN3bkFvMEdjbTZaNDZ6?= =?utf-8?B?U05WTXJmSG5uUm5SM0RDTHJCd2hyWkFXdUVLYTVqZnUvR1did3M4bUlwRDJt?= =?utf-8?B?YXl4czdOQm52elJDV1ZzQ1NtaTZzTSsxL0xsV1RHdkVqaldOcnhTRmVEaGc0?= =?utf-8?B?cVpjTjlQTzZoOGEzdDB0cjBGNHd4Z2NxZUdQZytYMFlVY0l5R3Zaa3c3aDR4?= =?utf-8?B?MHI5NGhiNTRHZzJMNnFDOWZPMnZ6MisrRXc4WGlGbm1IclU2N3dINDNYNW1P?= =?utf-8?B?UmVScHlwRWpWNndPSFk0S3JiVzgyS0V3aXZCMldHbWR0amlwa041WmcxWTZI?= =?utf-8?B?SXhXb3NPaFJ4Nk1keWdIQjZ6d1BnTFEvNW54eXkxbEdTa013YXhobUNNR2FR?= =?utf-8?B?Q05idnVOUnlTanc4Q2RONDFHYmNpRnhmaWNrbTJRSWRzQ3FaZWwrSEVYdUR3?= =?utf-8?B?bXhabmZ3MjRJTkE5U2s4OGhpdDZYcmhXTFZLNDBEZ3QzdFVJVkVzcXRibVVo?= =?utf-8?B?WWpGYjlrUXlNODFyK29jRWRIcVVqajZicVN0VDJaVldDUmNWZGhHTk80b3Ru?= =?utf-8?B?K0o5bGJPYlV6cUdzeVc1MmtYdlVOUmRVZXgxVmlINmc5NnJSV3N4bFRtY1NX?= =?utf-8?B?ZGw4VFBzbGdvWW4vRVBlU2lHZVQ5YW1LVGpNSVFFUk9DTmFFejlwems1emNq?= =?utf-8?B?YmpJYzVVQmlYaDM4M3RtczFFQ0hLbW8wNFl4TkxROUJ0WEpYekU3M2FqRDMv?= =?utf-8?B?OUhkbk1CL2h5SE1vaVkzMGNMcEo1MEg5MUV4dU9obEJ1SnVCRjl1OHBNVDFm?= =?utf-8?B?OUxTREh1K2tVbXBPR3pnS0lTVWdMeVd2WXhKZFdtYzcrYTc0Qjd3SnV2V3FW?= =?utf-8?B?K3pPaGJQMk5HbDFMcTBSbGZvWkJxZTQ5bDdEZ0F5bkdHUXN6bEFyVjZ4WTdB?= =?utf-8?B?Q3dSQmxIQ0hrZWVEN2x6dllXSUQxUm5yM1VlMFU1ay9zdzQzSFhBOWtNQ1du?= =?utf-8?B?bTZjVzk3eXI3Um0wNzFnU2lJdGtZeU15UUx5a2daQStsVjZVMzI5QzBnQy94?= =?utf-8?B?cGNHek4rRFR1WG9rcVRGUzhmNjhFa0NKWWs4UUZmVGlzT2pBMGlVVzBoRXls?= =?utf-8?B?NXovOGhkdlVheDdwT1R5cWRYWjNIdFhFa0F3dUFlOHdTeG81YXBORExhRWNV?= =?utf-8?B?WWlXcTNyeG5lcWZrQWdEcXlnZkZUMHpsTWt3RVRxT0NoTGdqNHhIZHVYNW9r?= =?utf-8?B?eEZ0REN4ZnhZOG40WGtjL1RQd0w4aWFTYjNidlFsbnB1N2V1R0xvY1hNdGRt?= =?utf-8?B?YzlNWFYrMHVSWUFaVGw4Tll3Q3YrQ1RVaHprRmU1RnpmWnNsb2x0NG1Kc2s0?= =?utf-8?B?ZWtoRmxVZXcrNzN2QUpVM0JFZllBM3JoVkVpQXphLzZHVDQyY0lXQTdVWEQ1?= =?utf-8?B?L2hWNmJnL2xtTUVnTitrVHU3cTRGNzlTSWd0cDBuai9tcG9RYVhUdU1Lc1Rw?= =?utf-8?B?M25RN0NmUjAwTktYQkN3UnN6eU03YWEySGlSd3liZXY5WEFYUTBheFJIQVJV?= =?utf-8?B?cjFUYUtOQ0VxY2FyMlZPc1JXUFI0Z0FDdWFjaFBJNE9JNk5pYi9xWEZ6SDFQ?= =?utf-8?B?TnBXeStQOHR3S0FXY0oyQVlXVmdUaVY5a21ydHpvWER3UjhBaE01djlXQ0h0?= =?utf-8?B?N3dGV29LeC9OekN3SVV2bXJNd2ZGamJwa3NEa1JJendEYTBRWmRRVitZQ3Rt?= =?utf-8?B?aFN5TnZOU0h6MCtFb3IwYytIWGltcFV4UHppWGRna2dIWXpGMWprQTVaMzZJ?= =?utf-8?B?dDZLYmk5V0o0OENRdFJ6UzZSUnVQY3lENG5rcWZBeFh4bXJocnJRMEdFd0E1?= =?utf-8?B?M1hFUTlhaTZRNlB6MFB4TWRhdjNEZzl3Z0dDVFhEc1hiSllWaHNhdHA4a3I4?= =?utf-8?B?N1M5SVZLM0ZOTm42M3NzSndFeVkvLytSQ2hoWjhUVFo5L2hmZGptdWswSFlh?= =?utf-8?B?S0RvVkFGSGowU1RuOHQ3TUlaY1BVUUNZTEYzY21hajkwTHdzKzJZS2RTMFJ0?= =?utf-8?B?bU5xNURyL0NJSTViVW5jQkRsYzUyK1I5OUZuTVh3S1pVRnBxUHhHbGJ2NkRN?= =?utf-8?Q?0IkZzZ289nuXNSQZ++zNoCHiz?= Content-ID: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: IA1PR11MB6193.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b12ef4b2-d7cf-49da-fd0d-08dbb37d3b61 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Sep 2023 10:44:25.1428 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3Er4VrMEKFlkgb1aGjFaRVeMxAGdWhHkostXTiwQesTJaJs2e+MiWK+weYBYRCOqcm0o0h7YLbsWYSRPVG4TZBFO3lM8Xqvw/uGoVgi2vKU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR11MB5057 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230912_034444_282084_B3533A73 X-CRM114-Status: GOOD ( 24.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 09/09/23 9:50 pm, claudiu beznea wrote: > [You don't often get email from claudiu.beznea@tuxon.dev. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Hi, Manikandan, > > On 8/25/23 15:54, Manikandan Muralidharan wrote: >> - XLCDC in SAM9X7 has different sets of registers and additional >> configuration bits when compared to previous HLCDC IP. Read/write >> operation on the controller registers is now separated using the >> XLCDC status flag. >> - HEO scaling, window resampling, Alpha blending, YUV-to-RGB >> conversion in XLCDC is derived and handled using additional >> configuration bits and registers. >> - Writing one to the Enable fields of each layer in LCD_ATTRE >> is required to reflect the values set in Configuration, FBA, Enable >> registers of each layer >> >> Signed-off-by: Manikandan Muralidharan >> Co-developed-by: Hari Prasath Gujulan Elango >> Signed-off-by: Hari Prasath Gujulan Elango >> Co-developed-by: Durai Manickam KR >> Signed-off-by: Durai Manickam KR >> --- >> .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 25 +- >> .../gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 333 +++++++++++++++--- >> 2 files changed, 299 insertions(+), 59 deletions(-) >> >> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c >> index cc5cf4c2faf7..4b11a1de8af4 100644 >> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c >> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c >> @@ -79,6 +79,7 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) >> unsigned int mask = ATMEL_HLCDC_CLKDIV_MASK | ATMEL_HLCDC_CLKPOL; >> unsigned int cfg = 0; >> int div, ret; >> + bool is_xlcdc = crtc->dc->desc->is_xlcdc; >> >> /* get encoder from crtc */ >> drm_for_each_encoder(en_iter, ddev) { >> @@ -164,10 +165,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) >> state = drm_crtc_state_to_atmel_hlcdc_crtc_state(c->state); >> cfg = state->output_mode << 8; >> >> - if (adj->flags & DRM_MODE_FLAG_NVSYNC) >> + if (!is_xlcdc && (adj->flags & DRM_MODE_FLAG_NVSYNC)) >> cfg |= ATMEL_HLCDC_VSPOL; >> >> - if (adj->flags & DRM_MODE_FLAG_NHSYNC) >> + if (!is_xlcdc && (adj->flags & DRM_MODE_FLAG_NHSYNC)) >> cfg |= ATMEL_HLCDC_HSPOL; >> >> regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5), >> @@ -202,6 +203,16 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, >> >> pm_runtime_get_sync(dev->dev); >> >> + if (crtc->dc->desc->is_xlcdc) { >> + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_CM); >> + regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, >> + !(status & ATMEL_XLCDC_CM), 10, 0); > > You may want to check the return value of regmap_read_poll_timeout(). > Otherwise your setup may fail. > > Also, regmap_read_poll_timeout() may sleep, the other settings in this > functions are done with bussy looping, is there a reason for that? >Hi Claudiu Not sure if a non-zero timeout_us coud be sufficient for this operation, considering the next power-up and power-down sequence following the current step. Any suggestion on the value of timeout_us is appreciable. >> + >> + regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_XLCDC_SD); >> + regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, >> + status & ATMEL_XLCDC_SD, 10, 0); > > Same here. > >> + } >> + >> regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP); >> while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && >> (status & ATMEL_HLCDC_DISP)) >> @@ -256,6 +267,16 @@ static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, >> !(status & ATMEL_HLCDC_DISP)) >> cpu_relax(); >> >> + if (crtc->dc->desc->is_xlcdc) { >> + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_CM); >> + regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, >> + status & ATMEL_XLCDC_CM, 10, 0); >> + >> + regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_XLCDC_SD); >> + regmap_read_poll_timeout(regmap, ATMEL_HLCDC_SR, status, >> + !(status & ATMEL_XLCDC_SD), 10, 0); >> + } >> + >> pm_runtime_put_sync(dev->dev); >> >> } >> diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c >> index daa508504f47..26caf4cddfa4 100644 >> --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c >> +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c >> @@ -330,11 +330,59 @@ static void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, >> yfactor)); >> } >> >> +static void atmel_xlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, >> + struct atmel_hlcdc_plane_state *state) >> +{ >> + const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; >> + u32 xfactor, yfactor; >> + >> + if (!desc->layout.scaler_config) >> + return; >> + >> + if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { >> + atmel_hlcdc_layer_write_cfg(&plane->layer, >> + desc->layout.scaler_config, 0); >> + return; >> + } >> + >> + /* xfactor = round[(2^20 * XMEMSIZE)/XSIZE)] */ >> + xfactor = (u32)(((1 << 20) * state->src_w) / state->crtc_w); > > Could ((1 << 20) * state->src_w) overflow? It is within the limits, state->src_w will contain a 11bit reg value at max. > >> + >> + /* yfactor = round[(2^20 * YMEMSIZE)/YSIZE)] */ >> + yfactor = (u32)(((1 << 20) * state->src_h) / state->crtc_h); > > Same here. > >> + >> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config, >> + ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE | >> + ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE | >> + ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE | >> + ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE); >> + >> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 1, >> + yfactor); >> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 3, >> + xfactor); >> + >> + /* As per YCbCr window resampling configuration */ >> + if (state->base.fb->format->format == DRM_FORMAT_YUV420) { >> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, >> + yfactor / 2); >> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4, >> + xfactor / 2); >> + } else { >> + /* As per ARGB window resampling configuration */ >> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, >> + yfactor); >> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4, >> + xfactor); >> + } > > This can be written as follows: > if (state->base.fb->format->format == DRM_FORMAT_YUV420) { > yfactor /= 2); > xfactor /= 2); > } > atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 2, > yfactor); > atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.scaler_config + 4, > xfactor); > > > >> +} >> + >> static void >> atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, >> struct atmel_hlcdc_plane_state *state) >> { >> const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; >> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; >> >> if (desc->layout.size) >> atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.size, >> @@ -352,7 +400,10 @@ atmel_hlcdc_plane_update_pos_and_size(struct atmel_hlcdc_plane *plane, >> ATMEL_HLCDC_LAYER_POS(state->crtc_x, >> state->crtc_y)); >> >> - atmel_hlcdc_plane_setup_scaler(plane, state); >> + if (dc->desc->is_xlcdc) >> + atmel_xlcdc_plane_setup_scaler(plane, state); >> + else >> + atmel_hlcdc_plane_setup_scaler(plane, state); > > What if you embedd the plane_setup_scaller function in struct > atmel_hlcdc_dc_desc and define per lcdc variant the proper function you can > have here something like: > dc->desc->plane_setup_scaler(); > > This is valid for other places in this patch (see below). Sure, I will try to incoperate this change. > >> } >> >> static void >> @@ -393,6 +444,40 @@ atmel_hlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, >> cfg); >> } >> >> +static void >> +atmel_xlcdc_plane_update_general_settings(struct atmel_hlcdc_plane *plane, >> + struct atmel_hlcdc_plane_state *state) >> +{ >> + unsigned int cfg; >> + const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; >> + const struct drm_format_info *format = state->base.fb->format; >> + >> + atmel_hlcdc_layer_write_cfg(&plane->layer, ATMEL_XLCDC_LAYER_DMA_CFG, >> + ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 | state->ahb_id); >> + >> + cfg = ATMEL_XLCDC_LAYER_DMA | ATMEL_XLCDC_LAYER_REP; >> + >> + if (plane->base.type != DRM_PLANE_TYPE_PRIMARY) { >> + /* >> + * Alpha Blending bits specific to SAM9X7 SoC >> + */ >> + cfg |= ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS | >> + ATMEL_XLCDC_LAYER_SFACTA_ONE | >> + ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS | >> + ATMEL_XLCDC_LAYER_DFACTA_ONE; >> + if (format->has_alpha) >> + cfg |= ATMEL_XLCDC_LAYER_A0(0xff); >> + else >> + cfg |= ATMEL_XLCDC_LAYER_A0(state->base.alpha); >> + } >> + >> + if (state->disc_h && state->disc_w) >> + cfg |= ATMEL_XLCDC_LAYER_DISCEN; >> + >> + atmel_hlcdc_layer_write_cfg(&plane->layer, desc->layout.general_config, >> + cfg); >> +} >> + >> static void atmel_hlcdc_plane_update_format(struct atmel_hlcdc_plane *plane, >> struct atmel_hlcdc_plane_state *state) >> { >> @@ -437,36 +522,55 @@ static void atmel_hlcdc_plane_update_clut(struct atmel_hlcdc_plane *plane, >> } >> } >> >> +static void update_hlcdc_buffers(struct atmel_hlcdc_plane *plane, >> + struct atmel_hlcdc_plane_state *state, u32 sr, int i) >> +{ >> + atmel_hlcdc_layer_write_reg(&plane->layer, >> + ATMEL_HLCDC_LAYER_PLANE_HEAD(i), >> + state->dscrs[i]->self); >> + >> + if (!(sr & ATMEL_HLCDC_LAYER_EN)) { > > To avoid extra indenting: > if (sr & ATMEL_HLCDC_LAYER_EN) > return; > >> + atmel_hlcdc_layer_write_reg(&plane->layer, >> + ATMEL_HLCDC_LAYER_PLANE_ADDR(i), >> + state->dscrs[i]->addr); >> + atmel_hlcdc_layer_write_reg(&plane->layer, >> + ATMEL_HLCDC_LAYER_PLANE_CTRL(i), >> + state->dscrs[i]->ctrl); >> + atmel_hlcdc_layer_write_reg(&plane->layer, >> + ATMEL_HLCDC_LAYER_PLANE_NEXT(i), >> + state->dscrs[i]->self); >> + } >> +} >> + >> +static void update_xlcdc_buffers(struct atmel_hlcdc_plane *plane, >> + struct atmel_hlcdc_plane_state *state, int i) >> +{ >> + atmel_hlcdc_layer_write_reg(&plane->layer, >> + ATMEL_XLCDC_LAYER_PLANE_ADDR(i), >> + state->dscrs[i]->addr); >> +} >> + >> static void atmel_hlcdc_plane_update_buffers(struct atmel_hlcdc_plane *plane, >> - struct atmel_hlcdc_plane_state *state) >> + struct atmel_hlcdc_plane_state *state) > > update_hlcdc_buffers() and update_xlcdc_buffers() could also be members in > the struct atmel_hlcdc_dc_desc and called accordingly where needed w/o > checking is_xlcdc. > >> { >> const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; >> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; >> struct drm_framebuffer *fb = state->base.fb; >> u32 sr; >> int i; >> >> - sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); >> + if (!dc->desc->is_xlcdc) >> + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); >> >> for (i = 0; i < state->nplanes; i++) { >> struct drm_gem_dma_object *gem = drm_fb_dma_get_gem_obj(fb, i); >> >> state->dscrs[i]->addr = gem->dma_addr + state->offsets[i]; >> >> - atmel_hlcdc_layer_write_reg(&plane->layer, >> - ATMEL_HLCDC_LAYER_PLANE_HEAD(i), >> - state->dscrs[i]->self); >> - >> - if (!(sr & ATMEL_HLCDC_LAYER_EN)) { >> - atmel_hlcdc_layer_write_reg(&plane->layer, >> - ATMEL_HLCDC_LAYER_PLANE_ADDR(i), >> - state->dscrs[i]->addr); >> - atmel_hlcdc_layer_write_reg(&plane->layer, >> - ATMEL_HLCDC_LAYER_PLANE_CTRL(i), >> - state->dscrs[i]->ctrl); >> - atmel_hlcdc_layer_write_reg(&plane->layer, >> - ATMEL_HLCDC_LAYER_PLANE_NEXT(i), >> - state->dscrs[i]->self); >> - } >> + if (dc->desc->is_xlcdc) >> + update_xlcdc_buffers(plane, state, i); >> + else >> + update_hlcdc_buffers(plane, state, sr, i); > > And here you can have something like: > dc->desc->update_lcdc_buffers(); >> >> if (desc->layout.xstride[i]) >> atmel_hlcdc_layer_write_cfg(&plane->layer, >> @@ -712,11 +816,8 @@ static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, >> return 0; >> } >> >> -static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, >> - struct drm_atomic_state *state) >> +static void hlcdc_atomic_disable(struct atmel_hlcdc_plane *plane) >> { >> - struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); >> - >> /* Disable interrupts */ >> atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IDR, >> 0xffffffff); >> @@ -731,6 +832,72 @@ static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, >> atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); >> } >> >> +static void xlcdc_atomic_disable(struct atmel_hlcdc_plane *plane) >> +{ >> + /* Disable interrupts */ >> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IDR, >> + 0xffffffff); >> + >> + /* Disable the layer */ >> + atmel_hlcdc_layer_write_reg(&plane->layer, >> + ATMEL_XLCDC_LAYER_ENR, 0); >> + >> + /* Clear all pending interrupts */ >> + atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR); >> +} >> + >> +static void atmel_hlcdc_plane_atomic_disable(struct drm_plane *p, >> + struct drm_atomic_state *state) >> +{ >> + struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); >> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; >> + >> + if (dc->desc->is_xlcdc) >> + xlcdc_atomic_disable(plane); >> + else >> + hlcdc_atomic_disable(plane); > > dc->desc->lcdc_atomic_disable(); > >> +} >> + >> +static void hlcdc_atomic_update(struct atmel_hlcdc_plane *plane) >> +{ >> + u32 sr; >> + >> + /* Enable the overrun interrupts. */ >> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, >> + ATMEL_HLCDC_LAYER_OVR_IRQ(0) | >> + ATMEL_HLCDC_LAYER_OVR_IRQ(1) | >> + ATMEL_HLCDC_LAYER_OVR_IRQ(2)); >> + >> + /* Apply the new config at the next SOF event. */ >> + sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); >> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, >> + ATMEL_HLCDC_LAYER_UPDATE | >> + (sr & ATMEL_HLCDC_LAYER_EN ? >> + ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); >> +} >> + >> +static void xlcdc_atomic_update(struct atmel_hlcdc_plane *plane, >> + struct atmel_hlcdc_dc *dc) >> +{ >> + /* Enable the overrun interrupts. */ >> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_IER, >> + ATMEL_XLCDC_LAYER_OVR_IRQ(0) | >> + ATMEL_XLCDC_LAYER_OVR_IRQ(1) | >> + ATMEL_XLCDC_LAYER_OVR_IRQ(2)); >> + >> + atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_XLCDC_LAYER_ENR, >> + ATMEL_XLCDC_LAYER_EN); >> + >> + /* >> + * Updating XLCDC_xxxCFGx, XLCDC_xxxFBA and XLCDC_xxxEN, >> + * (where xxx indicates each layer) requires writing one to the >> + * Update Attribute field for each layer in LCDC_ATTRE register for SAM9X7. >> + */ >> + regmap_write(dc->hlcdc->regmap, ATMEL_XLCDC_ATTRE, ATMEL_XLCDC_BASE_UPDATE | >> + ATMEL_XLCDC_OVR1_UPDATE | ATMEL_XLCDC_OVR3_UPDATE | >> + ATMEL_XLCDC_HEO_UPDATE); >> +} >> + >> static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, >> struct drm_atomic_state *state) >> { >> @@ -739,7 +906,7 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, >> struct atmel_hlcdc_plane *plane = drm_plane_to_atmel_hlcdc_plane(p); >> struct atmel_hlcdc_plane_state *hstate = >> drm_plane_state_to_atmel_hlcdc_plane_state(new_s); >> - u32 sr; >> + struct atmel_hlcdc_dc *dc = p->dev->dev_private; >> >> if (!new_s->crtc || !new_s->fb) >> return; >> @@ -750,29 +917,67 @@ static void atmel_hlcdc_plane_atomic_update(struct drm_plane *p, >> } >> >> atmel_hlcdc_plane_update_pos_and_size(plane, hstate); >> - atmel_hlcdc_plane_update_general_settings(plane, hstate); >> + if (dc->desc->is_xlcdc) >> + atmel_xlcdc_plane_update_general_settings(plane, hstate); >> + else >> + atmel_hlcdc_plane_update_general_settings(plane, hstate); > > dc->desc->lcdc_plane_update_general_settigns(); > >> atmel_hlcdc_plane_update_format(plane, hstate); >> atmel_hlcdc_plane_update_clut(plane, hstate); >> atmel_hlcdc_plane_update_buffers(plane, hstate); >> atmel_hlcdc_plane_update_disc_area(plane, hstate); >> >> - /* Enable the overrun interrupts. */ >> - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_IER, >> - ATMEL_HLCDC_LAYER_OVR_IRQ(0) | >> - ATMEL_HLCDC_LAYER_OVR_IRQ(1) | >> - ATMEL_HLCDC_LAYER_OVR_IRQ(2)); >> + if (dc->desc->is_xlcdc) >> + xlcdc_atomic_update(plane, dc); >> + else >> + hlcdc_atomic_update(plane); > > dc->desc->lcdc_atomic_update(); > >> +} >> >> - /* Apply the new config at the next SOF event. */ >> - sr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHSR); >> - atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHER, >> - ATMEL_HLCDC_LAYER_UPDATE | >> - (sr & ATMEL_HLCDC_LAYER_EN ? >> - ATMEL_HLCDC_LAYER_A2Q : ATMEL_HLCDC_LAYER_EN)); >> +u32 hlcdc_csc_coeffs[] = { >> + 0x4c900091, >> + 0x7a5f5090, >> + 0x40040890 >> +}; > > You can move this in function where it is used and declare it static. > >> + >> +u32 xlcdc_csc_coeffs[] = { >> + 0x00000488, >> + 0x00000648, >> + 0x1EA00480, >> + 0x00001D28, >> + 0x08100480, >> + 0x00000000, >> + 0x00000007 >> +}; > > Same here. > >> + >> +static void hlcdc_csc_init(struct atmel_hlcdc_plane *plane, >> + const struct atmel_hlcdc_layer_desc *desc) >> +{ >> + /* >> + * TODO: declare a "yuv-to-rgb-conv-factors" property to let >> + * userspace modify these factors (using a BLOB property ?). >> + */ >> + for (int i = 0; i < ARRAY_SIZE(hlcdc_csc_coeffs); i++) > > { at the end of for statement. > >> + atmel_hlcdc_layer_write_cfg(&plane->layer, >> + desc->layout.csc + i, >> + hlcdc_csc_coeffs[i]); > > } here > >> +} >> + >> +static void xlcdc_csc_init(struct atmel_hlcdc_plane *plane, >> + const struct atmel_hlcdc_layer_desc *desc) >> +{ >> + /* >> + * yuv-to-rgb-conv-factors are now defined from LCDC_HEOCFG16 to >> + * LCDC_HEOCFG21 registers in SAM9X7. >> + */ >> + for (int i = 0; i < ARRAY_SIZE(xlcdc_csc_coeffs); i++) >> + atmel_hlcdc_layer_write_cfg(&plane->layer, >> + desc->layout.csc + i, >> + xlcdc_csc_coeffs[i]); > > Ditto > >> } >> >> static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) >> { >> const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; >> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; >> >> if (desc->type == ATMEL_HLCDC_OVERLAY_LAYER || >> desc->type == ATMEL_HLCDC_CURSOR_LAYER) { >> @@ -796,31 +1001,19 @@ static int atmel_hlcdc_plane_init_properties(struct atmel_hlcdc_plane *plane) >> return ret; >> } >> >> - if (desc->layout.csc) { >> - /* >> - * TODO: decare a "yuv-to-rgb-conv-factors" property to let >> - * userspace modify these factors (using a BLOB property ?). >> - */ >> - atmel_hlcdc_layer_write_cfg(&plane->layer, >> - desc->layout.csc, >> - 0x4c900091); >> - atmel_hlcdc_layer_write_cfg(&plane->layer, >> - desc->layout.csc + 1, >> - 0x7a5f5090); >> - atmel_hlcdc_layer_write_cfg(&plane->layer, >> - desc->layout.csc + 2, >> - 0x40040890); >> - } >> + if (dc->desc->is_xlcdc && desc->layout.csc) >> + xlcdc_csc_init(plane, desc); >> + else >> + if (desc->layout.csc) >> + hlcdc_csc_init(plane, desc); > > if (desc->layout.csc) > dc->desc->lcdc_csc_init(); > >> >> return 0; >> } >> >> -void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) >> +static void hlcdc_irq_dbg(struct atmel_hlcdc_plane *plane, >> + const struct atmel_hlcdc_layer_desc *desc) >> { >> - const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; >> - u32 isr; >> - >> - isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); >> + u32 isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); >> >> /* >> * There's not much we can do in case of overrun except informing >> @@ -830,8 +1023,34 @@ void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) >> if (isr & >> (ATMEL_HLCDC_LAYER_OVR_IRQ(0) | ATMEL_HLCDC_LAYER_OVR_IRQ(1) | >> ATMEL_HLCDC_LAYER_OVR_IRQ(2))) >> - dev_dbg(plane->base.dev->dev, "overrun on plane %s\n", >> - desc->name); >> + pr_warn("%s: overrun on plane %s\n", __func__, desc->name); > > Why changing to pr_warn? why not dev_warn, if any? > >> +} >> + >> +static void xlcdc_irq_dbg(struct atmel_hlcdc_plane *plane, >> + const struct atmel_hlcdc_layer_desc *desc) >> +{ >> + u32 isr = atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_XLCDC_LAYER_ISR); >> + >> + /* >> + * There's not much we can do in case of overrun except informing >> + * the user. However, we are in interrupt context here, hence the >> + * use of dev_dbg(). >> + */ >> + if (isr & >> + (ATMEL_XLCDC_LAYER_OVR_IRQ(0) | ATMEL_XLCDC_LAYER_OVR_IRQ(1) | >> + ATMEL_XLCDC_LAYER_OVR_IRQ(2))) >> + pr_warn("%s: overrun on plane %s\n", __func__, desc->name); > > dev_warn() ? > >> +} >> + >> +void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane) >> +{ >> + const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; >> + struct atmel_hlcdc_dc *dc = plane->base.dev->dev_private; >> + >> + if (dc->desc->is_xlcdc) >> + xlcdc_irq_dbg(plane, desc); >> + else >> + hlcdc_irq_dbg(plane, desc); > > dc->desc->lcdc_irq_dbg() ? > >> } >> >> static const struct drm_plane_helper_funcs atmel_hlcdc_layer_plane_helper_funcs = { -- Thanks and Regards, Manikandan M. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel