From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97774C55178 for ; Fri, 6 Nov 2020 12:19:02 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F013D20715 for ; Fri, 6 Nov 2020 12:19:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="2ofZihr4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F013D20715 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GNasVFdEPglGCcySWeXlift3J8HyuTt4KWlHYRiIDIc=; b=2ofZihr4pwldyh+HyMr3J6Cqf C4UQGrYaY1wldCnp3/F6w6gS55XXTyQjIHe3hQhtcBVU07EHIS1ag7u9hi/CyeHeWf7VCxi/cmXMc /II2nSMHP3X80Pp0Mpp+Od937j4hNipeZOyUWcjufjzShj3hO3xJH3Cu0S6zx1nxHKk7s8tDJ1Txk Z3gOHzAHrAY4ZwS1dXHtxd/v27KbMAP3e8xuzwGDASErFUWUr5KZon7glD/205SGFaIV6wPZJkbel v1PCWo+KnxO9YQjLMD0Mvq2Knk1tyOwySS9ZZhAEn4j38mGAR2jb8wdyFZz8jSDlSwcWMIM1mOvD7 hNcOjW7dA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kb0hS-0001Tp-Le; Fri, 06 Nov 2020 12:18:38 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kb0hP-0001Sv-KF for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 12:18:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C84DE1474; Fri, 6 Nov 2020 04:18:34 -0800 (PST) Received: from [10.57.20.162] (unknown [10.57.20.162]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4B6BB3F718; Fri, 6 Nov 2020 04:18:33 -0800 (PST) Subject: Re: [PATCH] arm64: errata: Fix handling of 1418040 with late CPU onlining To: Will Deacon , linux-arm-kernel@lists.infradead.org References: <20201106114952.10032-1-will@kernel.org> From: Suzuki K Poulose Message-ID: Date: Fri, 6 Nov 2020 12:18:32 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <20201106114952.10032-1-will@kernel.org> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_071835_790474_8A95DA95 X-CRM114-Status: GOOD ( 25.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Sai Prakash Ranjan , Marc Zyngier , Stephen Boyd , Catalin Marinas , kernel-team@android.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On 11/6/20 11:49 AM, Will Deacon wrote: > In a surprising turn of events, it transpires that CPU capabilities > configured as ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE are never set as the > result of late-onlining. Therefore our handling of erratum 1418040 does > not get activated if it is not required by any of the boot CPUs, even > though we allow late-onlining of an affected CPU. The capability state is not altered after the SMP boot for all types of caps. The weak caps are there to allow a late CPU to turn online without getting "banned". This may be something we could relax with a new flag in the scope. > > In order to get things working again, replace the cpus_have_const_cap() > invocation with an explicit check for the current CPU using > this_cpu_has_cap(). > > Cc: Marc Zyngier > Cc: Sai Prakash Ranjan > Cc: Stephen Boyd > Cc: Catalin Marinas > Cc: Mark Rutland > Cc: Suzuki Poulose > Signed-off-by: Will Deacon > --- > > Found by code inspection and compile-tested only, so I would really > appreciate a second look. > > arch/arm64/include/asm/cpufeature.h | 2 ++ > arch/arm64/kernel/process.c | 5 ++--- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index f7e7144af174..c59c16a6ea8b 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -268,6 +268,8 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; > /* > * CPU feature detected at boot time based on feature of one or more CPUs. > * All possible conflicts for a late CPU are ignored. > + * NOTE: this means that a late CPU with the feature will *not* cause the > + * capability to be advertised by cpus_have_*cap()! This comment applies to all the types, so it may be confusing. And the comment already mentions that the feature is detected at boot time. > */ > #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \ > (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ > diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c > index 4784011cecac..a47a40ec6ad9 100644 > --- a/arch/arm64/kernel/process.c > +++ b/arch/arm64/kernel/process.c > @@ -522,14 +522,13 @@ static void erratum_1418040_thread_switch(struct task_struct *prev, > bool prev32, next32; > u64 val; > > - if (!(IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) && > - cpus_have_const_cap(ARM64_WORKAROUND_1418040))) > + if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040)) > return; > > prev32 = is_compat_thread(task_thread_info(prev)); > next32 = is_compat_thread(task_thread_info(next)); > > - if (prev32 == next32) > + if (prev32 == next32 || !this_cpu_has_cap(ARM64_WORKAROUND_1418040)) > return; > > val = read_sysreg(cntkctl_el1); > This change as such looks good to me. Reviewed-by: Suzuki K Poulose _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel