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Mon, 12 Aug 2019 15:38:34 +0000 From: To: , , , , , , , Subject: Re: [PATCH 2/2] ARM: dts: at91: sama5d27_som1_ek: add mmc capabilities for SDMMC0 Thread-Topic: [PATCH 2/2] ARM: dts: at91: sama5d27_som1_ek: add mmc capabilities for SDMMC0 Thread-Index: AQHVTcREWHJkbws9ckOkZIu1sPO5NabxMeQAgAAEQACAASQ2AIAFUKOA Date: Mon, 12 Aug 2019 15:38:34 +0000 Message-ID: References: <1565252928-28994-1-git-send-email-eugen.hristev@microchip.com> <1565252928-28994-2-git-send-email-eugen.hristev@microchip.com> <20190808124217.wrmcxohw5i6ju2qe@M43218.corp.atmel.com> <04fd74c3-a828-1064-b77b-f3de07a26190@intel.com> <20190809062322.syuieymdqjs4e7lh@M43218.corp.atmel.com> In-Reply-To: <20190809062322.syuieymdqjs4e7lh@M43218.corp.atmel.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR08CA0266.eurprd08.prod.outlook.com (2603:10a6:803:dc::39) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-ms-exchange-messagesentrepresentingtype: 1 x-tagtoolbar-keys: D20190812183317755 x-originating-ip: [94.177.32.154] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c052edc5-a8a9-4649-7123-08d71f3b2274 x-microsoft-antispam: BCL:0; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 09.08.2019 09:23, Ludovic Desroches wrote: > On Thu, Aug 08, 2019 at 03:57:30PM +0300, Adrian Hunter wrote: >> On 8/08/19 3:42 PM, Ludovic Desroches wrote: >>> On Thu, Aug 08, 2019 at 10:35:43AM +0200, Eugen Hristev - M18282 wrote: >>>> From: Eugen Hristev >>>> >>>> Add mmc capabilities for SDMMC0 for this board. >>>> With this enabled, eMMC connected card is detected as: >>>> >>>> mmc0: new DDR MMC card at address 0001 >>>> >>>> Signed-off-by: Eugen Hristev >>> Acked-by: Ludovic Desroches >>> >>> I am interested to have the some insights about the use of sd-uhs-* >>> properties. >>> >>> Our IP can't deal with 1V8 by itself. It has a 1V8SEL signal which can >>> be used as the logic control input of a mux. So even if the IP claims >>> to support UHS modes, it depends on the board. >>> >>> Are the sd-uhs-* properties a way to deal with this? I tend to think no >>> as sdhci_setup_host() will set the caps depending on the content of the >>> capabilities register. Do we have to use the SDHCI_QUIRK_MISSING_CAPS >>> quirk or sdhci-caps/sdhci-caps-mask? >> >> There is "no-1-8-v" which it looks like sdhci-of-at91.c already supports: >> >> sdhci_at91_probe() -> sdhci_get_of_property() -> sdhci_get_property() >> >> if (device_property_present(dev, "no-1-8-v")) >> host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; >> > > Right, I forgot this property. Thanks. > > Eugen, do you see cases we can't cover with this property? Hi, For current requirements and driver support, this should be enough. I noticed one thing regarding SD-Cards, if I add property sd-uhs-sdr104 the class 10 uhs1 cards are detected as SDR104 . Without this property they are detected as DDR50. Any idea why the difference ? The controller does not claim to have SDR104 support ? We should add it ? Eugen > > Regards > > Ludovic > >> >>> >>> Regards >>> >>> Ludovic >>> >>>> --- >>>> arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 1 + >>>> 1 file changed, 1 insertion(+) >>>> >>>> diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts >>>> index 149e539..194b3a3 100644 >>>> --- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts >>>> +++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts >>>> @@ -54,6 +54,7 @@ >>>> >>>> sdmmc0: sdio-host@a0000000 { >>>> bus-width = <8>; >>>> + mmc-ddr-3_3v; >>>> pinctrl-names = "default"; >>>> pinctrl-0 = <&pinctrl_sdmmc0_default>; >>>> status = "okay"; >>>> -- >>>> 2.7.4 >>>> >>> >> > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel