From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD1FCC11F68 for ; Fri, 2 Jul 2021 17:04:40 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 82A34613E0 for ; Fri, 2 Jul 2021 17:04:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 82A34613E0 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:Cc:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CFMoxtyvAMMKbwYNfwSnZIiL9D1kAPyBChzhDiQUNMw=; b=xIE3BoVmm+lG4Y J/BjV+7Q8sQY3Ph5Hq91RLWIuqnEYVKyCr3hVynzZ1QGLXjfWNN4VpbeMAdJYFFoXddk1NvLKw1bS S7cB2QXpIGxa5shqC2RNnUSK58IrEFhCb2rdU/5ZpePzmbN4bD1D92hB1ZN94VxQIncbxmOID0oPl oztqyibRxd+B5jw8e4EjxkaKsjKF4acuuEXxAHj5zWfLjZ954XGMcCIYbmqeXu+YCNJV41u2Narjs qj+ZIA5ORQaTrT07/tx3wjtcCcFrFBP9LeIVYsq5h1WrNN6X1IcoA0dVQOmbrbTh6niFxvGaoY7Qb zC7UXm3nFTHMgCM2AAkQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lzMZA-003agF-Sk; Fri, 02 Jul 2021 17:03:00 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lzMZ6-003afb-FV for linux-arm-kernel@lists.infradead.org; Fri, 02 Jul 2021 17:02:58 +0000 Received: from gallifrey.ext.pengutronix.de ([2001:67c:670:201:5054:ff:fe8d:eefb] helo=[IPv6:::1]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lzMZ1-0006Ec-UV; Fri, 02 Jul 2021 19:02:52 +0200 Message-ID: Subject: Re: [PATCH 1/2] soc: imx: gpcv2: Turn domain->pgc into bitfield From: Lucas Stach To: Marek Vasut , linux-arm-kernel@lists.infradead.org Cc: ch@denx.de, Frieder Schrempf , NXP Linux Team , Peng Fan , Shawn Guo Date: Fri, 02 Jul 2021 19:02:50 +0200 In-Reply-To: <20210630230129.237658-1-marex@denx.de> References: <20210630230129.237658-1-marex@denx.de> User-Agent: Evolution 3.40.1 (3.40.1-1.fc34) MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:201:5054:ff:fe8d:eefb X-SA-Exim-Mail-From: l.stach@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210702_100256_742987_0AFEA993 X-CRM114-Status: GOOD ( 25.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Am Donnerstag, dem 01.07.2021 um 01:01 +0200 schrieb Marek Vasut: > There is currently the MX8MM GPU domain, which is in fact a composite domain > for both GPU2D and GPU3D. To correctly configure this domain, it is necessary > to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same > time. This is currently not possible. > > Turn the domain->pgc from value into bitfield and use for_each_set_bit() to > iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL > register array. This way it is possible to configure all GPC_PGC_nCTRL > registers required in a particular domain. > > This is a preparatory patch, no functional change. Which tree was used to generate this patch? This does not apply on top of next or Shawn's imx/drivers tree and from a glance is at least missing the 8MN power domains. Regards, Lucas > > Signed-off-by: Marek Vasut > Cc: Frieder Schrempf > Cc: Lucas Stach > Cc: NXP Linux Team > Cc: Peng Fan > Cc: Shawn Guo > --- > drivers/soc/imx/gpcv2.c | 68 ++++++++++++++++++++++------------------- > 1 file changed, 36 insertions(+), 32 deletions(-) > > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c > index 388c4c729c95b..1cf23144d5378 100644 > --- a/drivers/soc/imx/gpcv2.c > +++ b/drivers/soc/imx/gpcv2.c > @@ -192,7 +192,7 @@ struct imx_pgc_domain { > struct clk_bulk_data *clks; > int num_clks; > > - unsigned int pgc; > + unsigned long pgc; > > const struct { > u32 pxx; > @@ -223,7 +223,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd) > static int imx_pgc_power_up(struct generic_pm_domain *genpd) > { > struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); > - u32 reg_val; > + u32 reg_val, pgc; > int ret; > > ret = pm_runtime_get_sync(domain->dev); > @@ -260,8 +260,10 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) > > if (domain->bits.pxx) { > /* disable power control */ > - regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), > - GPC_PGC_CTRL_PCR); > + for_each_set_bit(pgc, &domain->pgc, 32) { > + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc), > + GPC_PGC_CTRL_PCR); > + } > > /* request the domain to power up */ > regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, > @@ -330,7 +332,7 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) > static int imx_pgc_power_down(struct generic_pm_domain *genpd) > { > struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); > - u32 reg_val; > + u32 reg_val, pgc; > int ret; > > /* Enable reset clocks for all devices in the domain */ > @@ -357,8 +359,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) > > if (domain->bits.pxx) { > /* enable power control */ > - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), > - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); > + for_each_set_bit(pgc, &domain->pgc, 32) { > + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc), > + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); > + } > > /* request the domain to power down */ > regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, > @@ -408,7 +412,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { > .map = IMX7_MIPI_PHY_A_CORE_DOMAIN, > }, > .voltage = 1000000, > - .pgc = IMX7_PGC_MIPI, > + .pgc = BIT(IMX7_PGC_MIPI), > }, > > [IMX7_POWER_DOMAIN_PCIE_PHY] = { > @@ -420,7 +424,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { > .map = IMX7_PCIE_PHY_A_CORE_DOMAIN, > }, > .voltage = 1000000, > - .pgc = IMX7_PGC_PCIE, > + .pgc = BIT(IMX7_PGC_PCIE), > }, > > [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = { > @@ -432,7 +436,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { > .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN, > }, > .voltage = 1200000, > - .pgc = IMX7_PGC_USB_HSIC, > + .pgc = BIT(IMX7_PGC_USB_HSIC), > }, > }; > > @@ -467,7 +471,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_MIPI_SW_Pxx_REQ, > .map = IMX8M_MIPI_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_MIPI, > + .pgc = BIT(IMX8M_PGC_MIPI), > }, > > [IMX8M_POWER_DOMAIN_PCIE1] = { > @@ -478,7 +482,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_PCIE1_SW_Pxx_REQ, > .map = IMX8M_PCIE1_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_PCIE1, > + .pgc = BIT(IMX8M_PGC_PCIE1), > }, > > [IMX8M_POWER_DOMAIN_USB_OTG1] = { > @@ -489,7 +493,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_OTG1_SW_Pxx_REQ, > .map = IMX8M_OTG1_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_OTG1, > + .pgc = BIT(IMX8M_PGC_OTG1), > }, > > [IMX8M_POWER_DOMAIN_USB_OTG2] = { > @@ -500,7 +504,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_OTG2_SW_Pxx_REQ, > .map = IMX8M_OTG2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_OTG2, > + .pgc = BIT(IMX8M_PGC_OTG2), > }, > > [IMX8M_POWER_DOMAIN_DDR1] = { > @@ -511,7 +515,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_DDR1_SW_Pxx_REQ, > .map = IMX8M_DDR2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_DDR1, > + .pgc = BIT(IMX8M_PGC_DDR1), > }, > > [IMX8M_POWER_DOMAIN_GPU] = { > @@ -524,7 +528,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .hskreq = IMX8M_GPU_HSK_PWRDNREQN, > .hskack = IMX8M_GPU_HSK_PWRDNACKN, > }, > - .pgc = IMX8M_PGC_GPU, > + .pgc = BIT(IMX8M_PGC_GPU), > }, > > [IMX8M_POWER_DOMAIN_VPU] = { > @@ -537,7 +541,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .hskreq = IMX8M_VPU_HSK_PWRDNREQN, > .hskack = IMX8M_VPU_HSK_PWRDNACKN, > }, > - .pgc = IMX8M_PGC_VPU, > + .pgc = BIT(IMX8M_PGC_VPU), > }, > > [IMX8M_POWER_DOMAIN_DISP] = { > @@ -550,7 +554,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .hskreq = IMX8M_DISP_HSK_PWRDNREQN, > .hskack = IMX8M_DISP_HSK_PWRDNACKN, > }, > - .pgc = IMX8M_PGC_DISP, > + .pgc = BIT(IMX8M_PGC_DISP), > }, > > [IMX8M_POWER_DOMAIN_MIPI_CSI1] = { > @@ -561,7 +565,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ, > .map = IMX8M_MIPI_CSI1_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_MIPI_CSI1, > + .pgc = BIT(IMX8M_PGC_MIPI_CSI1), > }, > > [IMX8M_POWER_DOMAIN_MIPI_CSI2] = { > @@ -572,7 +576,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ, > .map = IMX8M_MIPI_CSI2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_MIPI_CSI2, > + .pgc = BIT(IMX8M_PGC_MIPI_CSI2), > }, > > [IMX8M_POWER_DOMAIN_PCIE2] = { > @@ -583,7 +587,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_PCIE2_SW_Pxx_REQ, > .map = IMX8M_PCIE2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_PCIE2, > + .pgc = BIT(IMX8M_PGC_PCIE2), > }, > }; > > @@ -646,7 +650,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_PCIE_SW_Pxx_REQ, > .map = IMX8MM_PCIE_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_PCIE, > + .pgc = BIT(IMX8MM_PGC_PCIE), > }, > > [IMX8MM_POWER_DOMAIN_OTG1] = { > @@ -657,7 +661,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_OTG1_SW_Pxx_REQ, > .map = IMX8MM_OTG1_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_OTG1, > + .pgc = BIT(IMX8MM_PGC_OTG1), > }, > > [IMX8MM_POWER_DOMAIN_OTG2] = { > @@ -668,7 +672,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_OTG2_SW_Pxx_REQ, > .map = IMX8MM_OTG2_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_OTG2, > + .pgc = BIT(IMX8MM_PGC_OTG2), > }, > > [IMX8MM_POWER_DOMAIN_GPUMIX] = { > @@ -681,7 +685,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN, > .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_GPUMIX, > + .pgc = BIT(IMX8MM_PGC_GPUMIX), > }, > > [IMX8MM_POWER_DOMAIN_GPU] = { > @@ -694,7 +698,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, > .hskack = IMX8MM_GPU_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_GPU2D, > + .pgc = BIT(IMX8MM_PGC_GPU2D), > /* Assert reset, power up domain, deassert reset */ > .reset_assert_early = true, > .reset_deassert_early = false, > @@ -710,7 +714,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN, > .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_VPUMIX, > + .pgc = BIT(IMX8MM_PGC_VPUMIX), > /* Assert reset, deassert reset, power up domain */ > .reset_assert_early = true, > .reset_deassert_early = true, > @@ -724,7 +728,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_VPUG1_SW_Pxx_REQ, > .map = IMX8MM_VPUG1_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_VPUG1, > + .pgc = BIT(IMX8MM_PGC_VPUG1), > }, > > [IMX8MM_POWER_DOMAIN_VPUG2] = { > @@ -735,7 +739,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_VPUG2_SW_Pxx_REQ, > .map = IMX8MM_VPUG2_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_VPUG2, > + .pgc = BIT(IMX8MM_PGC_VPUG2), > }, > > [IMX8MM_POWER_DOMAIN_VPUH1] = { > @@ -746,7 +750,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_VPUH1_SW_Pxx_REQ, > .map = IMX8MM_VPUH1_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_VPUH1, > + .pgc = BIT(IMX8MM_PGC_VPUH1), > }, > > [IMX8MM_POWER_DOMAIN_DISPMIX] = { > @@ -759,7 +763,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN, > .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_DISPMIX, > + .pgc = BIT(IMX8MM_PGC_DISPMIX), > }, > > [IMX8MM_POWER_DOMAIN_MIPI] = { > @@ -770,7 +774,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_MIPI_SW_Pxx_REQ, > .map = IMX8MM_MIPI_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_MIPI, > + .pgc = BIT(IMX8MM_PGC_MIPI), > }, > }; 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