Re: [PATCH v2 3/3] arm64: dts: imx8mp pollux: add displays for expansion board

[Yannic Moog <y.moog@phytec.de>]

On Wed, 2025-09-24 at 10:40 -0400, Frank Li wrote:
> On Wed, Sep 24, 2025 at 01:59:06PM +0200, Yannic Moog wrote:
> > The same displays that can be connected directly to the
> > imx8mp-phyboard-pollux can also be connected to the expansion board
> > PEB-AV-10. For displays connected to the expansion board, a second LVDS
> > channel of the i.MX 8M Plus SoC is used and only a single display
> > connected to the SoC LVDS display bridge at a given time is supported.
> > 
> > Signed-off-by: Yannic Moog <y.moog@phytec.de>
> > ---
> >  arch/arm64/boot/dts/freescale/Makefile             |  6 +++
> >  ...mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso | 45 ++++++++++++++++++++++
> >  ...8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso | 45 ++++++++++++++++++++++
> 
> I think you squash this to previous patch, or move previous patch dtso into
> this patch to show dtsi's usage.

I split the displays from the expansion board itself, because the expansion board can be used as is
without displays.
I had split the commits the same way in the past as to me they are different "topics".
If you insist I will squash, but my suggestion for a compromise is that I amend the commit
description for the expansion board patch to better explain why it exists as a dtsi file.

Yannic

> 
> Frank
> 
> >  3 files changed, 96 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> > index 9c121041128972d2239e2cc74df98b0bf7de1ac2..e4b097446440f41785dd1a0e5d354796e800ee76 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -222,11 +222,17 @@ imx8mp-phyboard-pollux-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-
> > rdk.dtb \
> >  	imx8mp-phyboard-pollux-etml1010g3dra.dtbo
> >  imx8mp-phyboard-pollux-peb-av-10-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
> >  	imx8mp-phyboard-pollux-peb-av-10.dtbo
> > +imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
> > +	imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtbo
> > +imx8mp-phyboard-pollux-peb-av-10-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
> > +	imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtbo
> >  imx8mp-phyboard-pollux-ph128800t006-dtbs += imx8mp-phyboard-pollux-rdk.dtb \
> >  	imx8mp-phyboard-pollux-ph128800t006.dtbo
> >  imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-
> > eth.dtbo
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-etml1010g3dra.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-ph128800t006.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb
> >  dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-basic.dtb
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso
> > b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..d71945430c801a0136a95d691af0cec64622a066
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-etml1010g3dra.dtso
> > @@ -0,0 +1,45 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (C) 2025 PHYTEC Messtechnik GmbH
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/clock/imx8mp-clock.h>
> > +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi"
> > +
> > +&backlight_lvds0 {
> > +	brightness-levels = <0 8 16 32 64 128 255>;
> > +	default-brightness-level = <8>;
> > +	enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
> > +	num-interpolated-steps = <2>;
> > +	pwms = <&pwm4 0 50000 0>;
> > +	status = "okay";
> > +};
> > +
> > +&lcdif2 {
> > +	status = "okay";
> > +};
> > +
> > +&lvds_bridge {
> > +	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
> > +	assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
> > +	/*
> > +	 * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
> > +	 * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout
> > +	 * engine can reach accurate pixel clock of exactly 72.4 MHz.
> > +	 */
> > +	assigned-clock-rates = <0>, <506800000>;
> > +	status = "okay";
> > +};
> > +
> > +&panel_lvds0 {
> > +	compatible = "edt,etml1010g3dra";
> > +	status = "okay";
> > +};
> > +
> > +&pwm4 {
> > +	status = "okay";
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso
> > b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..8ec4bbbbabb5cc7f5ae05d641fb5d14931250daf
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-peb-av-10-ph128800t006.dtso
> > @@ -0,0 +1,45 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (C) 2025 PHYTEC Messtechnik GmbH
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/clock/imx8mp-clock.h>
> > +#include "imx8mp-phyboard-pollux-peb-av-10.dtsi"
> > +
> > +&backlight_lvds0 {
> > +	brightness-levels = <0 8 16 32 64 128 255>;
> > +	default-brightness-level = <8>;
> > +	enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
> > +	num-interpolated-steps = <2>;
> > +	pwms = <&pwm4 0 66667 0>;
> > +	status = "okay";
> > +};
> > +
> > +&lcdif2 {
> > +	status = "okay";
> > +};
> > +
> > +&lvds_bridge {
> > +	assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
> > +	assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
> > +	/*
> > +	 * The LVDS panel uses 66.5 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to
> > +	 * 66.5 * 7 = 465.5 MHz so the LDB serializer and LCDIFv3 scanout
> > +	 * engine can reach accurate pixel clock of exactly 66.5 MHz.
> > +	 */
> > +	assigned-clock-rates = <0>, <465500000>;
> > +	status = "okay";
> > +};
> > +
> > +&panel_lvds0 {
> > +	compatible = "powertip,ph128800t006-zhc01";
> > +	status = "okay";
> > +};
> > +
> > +&pwm4 {
> > +	status = "okay";
> > +};
> > 
> > --
> > 2.51.0
> >