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Received: from KL1PR03MB7149.apcprd03.prod.outlook.com (2603:1096:820:ca::7) by OSQPR03MB8526.apcprd03.prod.outlook.com (2603:1096:604:280::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8813.26; Fri, 13 Jun 2025 09:39:07 +0000 Received: from KL1PR03MB7149.apcprd03.prod.outlook.com ([fe80::a311:33f6:519d:73bf]) by KL1PR03MB7149.apcprd03.prod.outlook.com ([fe80::a311:33f6:519d:73bf%3]) with mapi id 15.20.8813.036; Fri, 13 Jun 2025 09:39:05 +0000 Message-ID: Date: Fri, 13 Jun 2025 17:39:03 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 6/6] clk: meson: t7: add t7 clock peripherals controller driver To: Jerome Brunet Cc: Xianwei Zhao , Chuan Liu , Neil Armstrong , Kevin Hilman , Stephen Boyd , Michael Turquette , Dmitry Rokosov , robh+dt , Rob Herring , devicetree , linux-clk , linux-amlogic , linux-kernel , linux-arm-kernel References: <20250509074825.1933254-1-jian.hu@amlogic.com> <20250509074825.1933254-7-jian.hu@amlogic.com> <1jo6vvy63e.fsf@starbuckisacylon.baylibre.com> From: Jian Hu In-Reply-To: <1jo6vvy63e.fsf@starbuckisacylon.baylibre.com> Content-Type: text/plain; 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>> + >> +static const struct clk_parent_data t7_eth_rmii_parents[] = { >> + { .fw_name = "fdiv2", }, >> + { .fw_name = "rmii_pad", }, > Are you sure about that ? check the bindings Ok, rmii_pad is optional parent, I will update it in DT bindings. >> + >> +#define SPI_PWM_CLK_MUX(_name, _reg, _mask, _shift, _parent_data) { \ >> + .data = &(struct clk_regmap_mux_data) { \ >> + .offset = _reg, \ >> + .mask = _mask, \ >> + .shift = _shift, \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name "_sel", \ >> + .ops = &clk_regmap_mux_ops, \ >> + .parent_data = _parent_data, \ >> + .num_parents = ARRAY_SIZE(_parent_data), \ >> + }, \ >> +} >> + >> +#define SPI_PWM_CLK_DIV(_name, _reg, _shift, _width, _parent) { \ >> + .data = &(struct clk_regmap_div_data) { \ >> + .offset = _reg, \ >> + .shift = _shift, \ >> + .width = _width, \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name "_div", \ >> + .ops = &clk_regmap_divider_ops, \ >> + .parent_hws = (const struct clk_hw *[]) { \ >> + &_parent.hw \ >> + }, \ >> + .num_parents = 1, \ >> + .flags = CLK_SET_RATE_PARENT, \ >> + }, \ >> +} >> + >> +#define SPI_PWM_CLK_GATE(_name, _reg, _bit, _parent) { \ >> + .data = &(struct clk_regmap_gate_data) { \ >> + .offset = _reg, \ >> + .bit_idx = _bit, \ >> + }, \ >> + .hw.init = &(struct clk_init_data) { \ >> + .name = #_name, \ >> + .ops = &clk_regmap_gate_ops, \ >> + .parent_hws = (const struct clk_hw *[]) { \ >> + &_parent.hw \ >> + }, \ >> + .num_parents = 1, \ >> + .flags = CLK_SET_RATE_PARENT, \ >> + }, \ >> +} > > Again that something that has been repeated for way too long. > You'll wait for the clean-up to be done. If you want to help, you can > review and test the patch being sent. It may speed things up. I want to confirm here . you said the clean-up patch is not related to spi and pwm clocks, Right ? I can see the regmap drop table patch [0], is it the sending patch? [0]: https://patchwork.kernel.org/project/linux-amlogic/patch/20250120-amlogic-clk-drop-clk-regmap-tables-v3-0-126244146947@baylibre.com/ I will apply the regmap clean-up patch serial and verified it on T7. If not， Please correct me. >> + >> +static const struct clk_parent_data t7_spicc_parents[] = { >> + { .fw_name = "xtal", }, >> + { .fw_name = "sys", }, >> + { .fw_name = "fdiv4", }, >> + { .fw_name = "fdiv3", }, >> + { .fw_name = "fdiv2", }, >> + { .fw_name = "fdiv5", }, >> + { .fw_name = "fdiv7", }, >> + { .fw_name = "gp1", }, >> +}; >> + >> ...... >> +static struct clk_regmap t7_sys_gic = { >> + .data = &(struct clk_regmap_gate_data) { >> + .offset = CLKCTRL_SYS_CLK_EN0_REG2, >> + .bit_idx = 30, >> + }, >> + .hw.init = &(struct clk_init_data){ >> + .name = "t7_sys_gic", >> + .ops = &clk_regmap_gate_ops, >> + .parent_data = &(const struct clk_parent_data) { >> + .fw_name = "sys", >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, > Do you really intend to for the rate of the sys pll to be set through > this clock ? Ok, CLK_SET_RATE_PARENT is not necessary here, I will remove it. >> ...... > -- > Jerome