From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6AB4BD5C0C2 for ; Tue, 16 Dec 2025 08:52:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=2J5AadwEBdTwAWucvKupulv4Jg5vl93UuJXQSAqvTPc=; b=Cx++z/nbdd/qzudbf059zzaNBv FfCOUE6GRlUqVJpTMDAC5m4KU/PnSkIQgW2de72DPM6w7MvyTXX13tw1f82EpytMzhg8/BgF4OKUG O+5GjV2lQTdqQzFtlhZSFbfMPTaRP/8QAViSzoRn362GoeB8fOwOwMEsV7XHdFKNp7MMJAqDNA4C0 mwFY8Bqrt1HeQTFF3m+lJHmyIiLGuMg7P2bvFYJ1DRklzrSOaffmMRQyy+1YweRsV5BKfst62UM2p bD3z0P5AxHuoJ9ibNKiyXKe7XbJJm7t7sTxs3WlWx4Wol+bKIGTmgB16mxunEsmJsLOWO7OP/mtoA TVlQcPzA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vVQmr-00000004xCU-2beH; Tue, 16 Dec 2025 08:52:05 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vVQmq-00000004xCI-0RFd for linux-arm-kernel@lists.infradead.org; Tue, 16 Dec 2025 08:52:04 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 3FF0760010; Tue, 16 Dec 2025 08:52:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4CD6BC4CEF1; Tue, 16 Dec 2025 08:51:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765875123; bh=5yo5JqZWB7fW9gV7EpQXnHOSL2dm1tpCTiFS4yqKKJY=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=n/F1mud59bDspQ+N7JBK2BrasxGl7iffNcwcAG0O4e1SqcVQiwos9yL8uIG66HF1T vkiIBO0ydpAQWExnKTWSuLTtz2oretzZjqes8YCrfQUVLz+s3obZiHzkQdSlEz0v51 avGhZme8uCNMO+JlHdNhv7GkpkKdnivH4E+ikv+X/6fFQa3dWhdCvRLVhWWQEe+fbl 4eQ9NnGz/BwCXXjEfm4xDKjr2U4MTJEeyQZqCwOKtFxv3EmPJZaqWmFufCumv+Y+cB UqxemO+lsUxri/rcSaV9tHb55JKI/Fyz9Hzx5BoCg5wax3i4lYkThYyEn2W8G8i19t zhxl3xsEhrx6w== Message-ID: Date: Tue, 16 Dec 2025 09:51:56 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/11] dt-bindings: clock: qcom: document the Kaanapali GPU Clock Controller To: Taniya Das Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Jingyi Wang , Bryan O'Donoghue References: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> <20251125-kaanapali-mmcc-v2-v2-7-fb44e78f300b@oss.qualcomm.com> <20251126-elated-stoic-scorpion-25b630@kuoka> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 04/12/2025 07:49, Taniya Das wrote: >>> + power-domains: >>> + description: >>> + Power domains required for the clock controller to operate >>> + items: >>> + - description: GFX power domain >>> + - description: GMXC power domain >>> + - description: GPUCC(CX) power domain >>> + >>> + '#power-domain-cells': >> >> Power domain controllers do not belong to clocks, so this is: >> 1. Misplaced - wrong folder >> 2. Probably wrongly named. gxclkctl sounds like clock controller, but >> this is domain controller? >> > > The GFXCLKCTL is actually a clock controller which has PLLs, clocks and > Power domains (GDSC), but the requirement here is to use the GDSC from > the clock controller to recover the GPU firmware in case of any > failure/hangs. The rest of the resources of the clock controller are > being used by the firmware of GPU. The GDSC is a clock controller > resource and modeled from the clock controller drivers across chipsets. This should be somewhere explained. > >>> + const: 1 >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> +required: >>> + - compatible >>> + - reg >>> + - power-domains >>> + - '#power-domain-cells' >>> + >>> +unevaluatedProperties: false >>> + >>> +examples: >>> + - | >>> + #include >>> + soc { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + clock-controller@3d68024 { >>> + compatible = "qcom,kaanapali-gxclkctl"; >>> + reg = <0 0x3d68024 0x0 0x8>; >> >> Keep consistent hex, so first 0 -> 0x0. > > Sure, will fix this. > >> But the problem is that you defined a device for two registers, >> basically one domain. I have doubts now whether this is complete and >> real device. >> > > As the Linux GPU driver requires only the GDSC, I have mapped the region > which is required by the clock controller driver. If required, the > entire region can be mapped as well. Required is to properly describe the hardware, please read writing bindings doc. > >>> + power-domains = <&rpmhpd RPMHPD_GFX>, >>> + <&rpmhpd RPMHPD_GMXC>, >>> + <&gpucc 0>; >>> + #power-domain-cells = <1>; >> >> And cells 1 makes no sense in such case. >> > > We would like to leverage the existing common clock driver(GDSC) code to Fix the driver code if it cannot handle other cells. Your drivers do not matter for choices made in bindings. > register the power-domains and also maintain uniformity across chipsets > and consistency in consumer GDSC phandle usage. There is no such consistency rule. Don't make up your own rules. Best regards, Krzysztof