[PATCH 0/5] omap4: l2x0 fixes and cleanup

[PATCH 0/5] omap4: l2x0 fixes and cleanup

[Santosh Shilimkar]

This series is outcome of the below discussion thread.
	http://www.spinics.net/lists/arm-kernel/msg104254.html

The series in brief has following patches
	- adds PL310 aux-control register bitfields
	- Use these bitfields instead of hardcoded values as part of init
	- Enable PL310 intsruction, Data prefetch hints and  BRESP to 
		improve performance
	- Set share-override bit to avoid non-cached buffer corruption
	
Thanks to Nishant Menon for testing this series on OMAP4 panda using
the memspeed utility. Have boot tested this series on OMAP4 SDP with
omap2plus_defconfig.

The following changes since commit e53beacd23d9cb47590da6a7a7f6d417b941a994:
  Linus Torvalds (1):
        Linux 2.6.37-rc2

Mans Rullgard (1):
      omap4: l2x0: enable instruction and data prefetching

Santosh Shilimkar (4):
      ARM: l2x0: Add aux control register bitfields
      omap4: l2x0: Construct the AUXCTRL value using defines
      omap4: l2x0: Set share override bit
      omap4: l2x0: Enable early BRESP bit

 arch/arm/include/asm/hardware/cache-l2x0.h |   12 ++++++++++-
 arch/arm/mach-omap2/omap4-common.c         |   30 +++++++++++++++++++++------
 2 files changed, 34 insertions(+), 8 deletions(-)

[PATCH 1/5] ARM: l2x0: Add aux control register bitfields

[Santosh Shilimkar]

This patch adds the PL310 Auxiliary Control Register bitfields
so that SOC's can use these bit fields to construct the AUXCTRL
value to be passed/programmed instead of hardcoding it.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
---
 arch/arm/include/asm/hardware/cache-l2x0.h |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index cc42d5f..5aeec1e 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -59,7 +59,17 @@
 #define L2X0_CACHE_ID_PART_MASK		(0xf << 6)
 #define L2X0_CACHE_ID_PART_L210		(1 << 6)
 #define L2X0_CACHE_ID_PART_L310		(3 << 6)
-#define L2X0_AUX_CTRL_WAY_SIZE_MASK	(0x3 << 17)
+
+#define L2X0_AUX_CTRL_MASK			0xc0000fff
+#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT	16
+#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT		17
+#define L2X0_AUX_CTRL_WAY_SIZE_MASK		(0x3 << 17)
+#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT	22
+#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT		26
+#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT		27
+#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT	28
+#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT	29
+#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT		30
 
 #ifndef __ASSEMBLY__
 extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask);
-- 
1.6.0.4

[PATCH 2/5] omap4: l2x0: Construct the AUXCTRL value using defines

[Santosh Shilimkar]

This patch removes the hardcoded value of auxctrl value and
construct it using bitfields

Bit 25 is reserved and is always set to 1. Same value
of this bit is retained in this patch

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/omap4-common.c |   13 +++++++++++--
 1 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 2f89555..c814604 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -53,6 +53,8 @@ static void omap4_l2x0_disable(void)
 
 static int __init omap_l2_cache_init(void)
 {
+	u32 aux_ctrl = 0;
+
 	/*
 	 * To avoid code running on other OMAPs in
 	 * multi-omap builds
@@ -72,10 +74,17 @@ static int __init omap_l2_cache_init(void)
 	 * Way size - 32KB (es1.0)
 	 * Way size - 64KB (es2.0 +)
 	 */
+	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
+			(0x1 << 25) |
+			(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
+			(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
+
 	if (omap_rev() == OMAP4430_REV_ES1_0)
-		l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
 	else
-		l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
+		aux_ctrl |= 0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
+
+	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 
 	/*
 	 * Override default outer_cache.disable with a OMAP4
-- 
1.6.0.4

[PATCH 3/5] omap4: l2x0: enable instruction and data prefetching

[Santosh Shilimkar]

From: Mans Rullgard <mans@mansr.com>

Enabling L2 prefetching improves performance as shown on Panda
ES2.1 board with mem test, and it has measurable impact on
performances. I think we should consider it, even though it damages
"writes" a bit. (rebased to k.org)
Usually the prefetch is used at both levels together L1 + L2, however,
to enable the CP15 prefetch engines, these are under security, and on
GP devices, we cannot enable it(e.g. on PandaBoard). However, just
enabling PL310 prefetch seems to provide performance improvement,
as shown in the data below (from Ubuntu) and would be a great thing
to pull in.

What prefetch does is enable automatic next line prefetching. With this
enabled, whenever the PL310 receives a cachable read request, it
automatically prefetches the following cache line as well.

Measurement Data:
==
STOCK 10.10 WITHOUT PATCH

========================
~# ./memspeed
size    8388608 8192k 8M
offset  8388608, 0
buffers 0x2aaad000 0x2b2ad000
copy  libc          133 MB/s
copy  Android v5    273 MB/s
copy  Android NEON  235 MB/s
copy  INT32         116 MB/s
copy  ASM ARM       187 MB/s
copy  ASM VLDM 64   204 MB/s
copy  ASM VLDM 128  173 MB/s
copy  ASM VLD1      216 MB/s
read  ASM ARM       286 MB/s
read  ASM VLDM      242 MB/s
read  ASM VLD1      286 MB/s
write libc         1947 MB/s
write ASM ARM      1943 MB/s
write ASM VSTM     1942 MB/s
write ASM VST1     1935 MB/s

10.10 + PATCH
=============
~# ./memspeed
size    8388608 8192k 8M
offset  8388608, 0
buffers 0x2ab17000 0x2b317000
copy  libc          129 MB/s
copy  Android v5    256 MB/s
copy  Android NEON  356 MB/s
copy  INT32         127 MB/s
copy  ASM ARM       321 MB/s
copy  ASM VLDM 64   337 MB/s
copy  ASM VLDM 128  321 MB/s
copy  ASM VLD1      350 MB/s
read  ASM ARM       496 MB/s
read  ASM VLDM      470 MB/s
read  ASM VLD1      488 MB/s
write libc         1701 MB/s
write ASM ARM      1682 MB/s
write ASM VSTM     1693 MB/s
write ASM VST1     1681 MB/s

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/omap4-common.c |   17 +++++++++++------
 1 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index c814604..b3cea78 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -66,9 +66,6 @@ static int __init omap_l2_cache_init(void)
 	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
 	BUG_ON(!l2cache_base);
 
-	/* Enable PL310 L2 Cache controller */
-	omap_smc1(0x102, 0x1);
-
 	/*
 	 * 16-way associativity, parity disabled
 	 * Way size - 32KB (es1.0)
@@ -79,10 +76,18 @@ static int __init omap_l2_cache_init(void)
 			(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
 			(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
 
-	if (omap_rev() == OMAP4430_REV_ES1_0)
+	if (omap_rev() == OMAP4430_REV_ES1_0) {
 		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
-	else
-		aux_ctrl |= 0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
+	} else {
+		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
+			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT));
+	}
+	if (omap_rev() != OMAP4430_REV_ES1_0)
+		omap_smc1(0x109, aux_ctrl);
+
+	/* Enable PL310 L2 Cache controller */
+	omap_smc1(0x102, 0x1);
 
 	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 
-- 
1.6.0.4

[PATCH 4/5] omap4: l2x0: Set share override bit

[Santosh Shilimkar]

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/omap4-common.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index b3cea78..2006da1 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -80,6 +80,7 @@ static int __init omap_l2_cache_init(void)
 		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
 	} else {
 		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
+			(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
 			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
 			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT));
 	}
-- 
1.6.0.4

[PATCH 5/5] omap4: l2x0: Enable early BRESP bit

[Santosh Shilimkar]

The AXI protocol specifies that the write response can only
be sent back to an AXI master when the last write data has been
accepted. This optimization enables the PL310 to send the write
response of certain write transactions as soon as the store buffer
accepts the write address. This behavior is not compatible with
the AXI protocol and is disabled by default. You enable this
optimization by setting the Early BRESP Enable bit in the
Auxiliary Control Register (bit [30]).

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mans Rullgard <mans@mansr.com>
Tested-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/omap4-common.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 2006da1..e7a9b7f 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -82,7 +82,8 @@ static int __init omap_l2_cache_init(void)
 		aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
 			(1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
 			(1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
-			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT));
+			(1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+			(1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
 	}
 	if (omap_rev() != OMAP4430_REV_ES1_0)
 		omap_smc1(0x109, aux_ctrl);
-- 
1.6.0.4

[PATCH 5/5] omap4: l2x0: Enable early BRESP bit

[Måns Rullgård]

Santosh Shilimkar <santosh.shilimkar@ti.com> writes:

> The AXI protocol specifies that the write response can only
> be sent back to an AXI master when the last write data has been
> accepted. This optimization enables the PL310 to send the write
> response of certain write transactions as soon as the store buffer
> accepts the write address. This behavior is not compatible with
> the AXI protocol and is disabled by default. You enable this
> optimization by setting the Early BRESP Enable bit in the
> Auxiliary Control Register (bit [30]).

Did you measure the performance difference this makes, if any?

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH 5/5] omap4: l2x0: Enable early BRESP bit

[Santosh Shilimkar]

> -----Original Message-----
> From: M?ns Rullg?rd [mailto:mans at mansr.com]
> Sent: Saturday, November 20, 2010 12:02 AM
> To: Santosh Shilimkar
> Cc: linux-omap at vger.kernel.org; nm at ti.com; mans at mansr.com;
> tony at atomide.com; khilman at deeprootsystems.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH 5/5] omap4: l2x0: Enable early BRESP bit
>
> Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
>
> > The AXI protocol specifies that the write response can only
> > be sent back to an AXI master when the last write data has been
> > accepted. This optimization enables the PL310 to send the write
> > response of certain write transactions as soon as the store buffer
> > accepts the write address. This behavior is not compatible with
> > the AXI protocol and is disabled by default. You enable this
> > optimization by setting the Early BRESP Enable bit in the
> > Auxiliary Control Register (bit [30]).
>
> Did you measure the performance difference this makes, if any?
>
I didn't do any special runs for this bit alone. Just checked
with hardware team and they confirmed that you would gain a bit
on writes and it's good to enable it.

[PATCH 2/5] omap4: l2x0: Construct the AUXCTRL value using defines

[Kevin Hilman]

Santosh Shilimkar <santosh.shilimkar@ti.com> writes:

> This patch removes the hardcoded value of auxctrl value and
> construct it using bitfields
>
> Bit 25 is reserved and is always set to 1. Same value
> of this bit is retained in this patch

Is this OMAP specific, or is this ARM generic?

> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Tested-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm/mach-omap2/omap4-common.c |   13 +++++++++++--
>  1 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
> index 2f89555..c814604 100644
> --- a/arch/arm/mach-omap2/omap4-common.c
> +++ b/arch/arm/mach-omap2/omap4-common.c
> @@ -53,6 +53,8 @@ static void omap4_l2x0_disable(void)
>  
>  static int __init omap_l2_cache_init(void)
>  {
> +	u32 aux_ctrl = 0;
> +
>  	/*
>  	 * To avoid code running on other OMAPs in
>  	 * multi-omap builds
> @@ -72,10 +74,17 @@ static int __init omap_l2_cache_init(void)
>  	 * Way size - 32KB (es1.0)
>  	 * Way size - 64KB (es2.0 +)
>  	 */
> +	aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
> +			(0x1 << 25) |

it doesn't look right to have a single hard-coded constant here among
the others.   Either give this a name (RESERVED_ALWAYS_1, or something)
or add a comment to the code like is done in the changelog.

> +			(0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
> +			(0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
> +
>  	if (omap_rev() == OMAP4430_REV_ES1_0)
> -		l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
> +		aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
>  	else
> -		l2x0_init(l2cache_base, 0x0e070000, 0xc0000fff);
> +		aux_ctrl |= 0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
> +
> +	l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
>  
>  	/*
>  	 * Override default outer_cache.disable with a OMAP4

Kevin

[PATCH 2/5] omap4: l2x0: Construct the AUXCTRL value using defines

[Måns Rullgård]

Kevin Hilman <khilman@deeprootsystems.com> writes:

> Santosh Shilimkar <santosh.shilimkar@ti.com> writes:
>
>> This patch removes the hardcoded value of auxctrl value and
>> construct it using bitfields
>>
>> Bit 25 is reserved and is always set to 1. Same value
>> of this bit is retained in this patch
>
> Is this OMAP specific, or is this ARM generic?

The bit fields are generic PL310.  It has to be set from OMAP code due
to the ROM call.

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH 1/5] ARM: l2x0: Add aux control register bitfields

[Catalin Marinas]

On Fri, 2010-11-19 at 17:31 +0000, Santosh Shilimkar wrote:
> This patch adds the PL310 Auxiliary Control Register bitfields
> so that SOC's can use these bit fields to construct the AUXCTRL
> value to be passed/programmed instead of hardcoding it.
> 
> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

[PATCH 0/5] omap4: l2x0 fixes and cleanup

[Santosh Shilimkar]

Tony,
> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> Sent: Friday, November 19, 2010 11:01 PM
> To: linux-omap at vger.kernel.org
> Cc: nm at ti.com; mans at mansr.com; tony at atomide.com;
> khilman at deeprootsystems.com; linux-arm-kernel at lists.infradead.org;
Santosh
> Shilimkar
> Subject: [PATCH 0/5] omap4: l2x0 fixes and cleanup
>
> This series is outcome of the below discussion thread.
> 	http://www.spinics.net/lists/arm-kernel/msg104254.html
>
> The series in brief has following patches
> 	- adds PL310 aux-control register bitfields
> 	- Use these bitfields instead of hardcoded values as part of init
> 	- Enable PL310 intsruction, Data prefetch hints and  BRESP to
> 		improve performance
> 	- Set share-override bit to avoid non-cached buffer corruption
>
> Thanks to Nishant Menon for testing this series on OMAP4 panda using
> the memspeed utility. Have boot tested this series on OMAP4 SDP with
> omap2plus_defconfig.
>
How about merging this series in omap-testing if you are ok
with it. Patch  " ARM: l2x0: Add aux control register bitfields"
is already acked by Catalin.

> The following changes since commit
> e53beacd23d9cb47590da6a7a7f6d417b941a994:
>   Linus Torvalds (1):
>         Linux 2.6.37-rc2
>
> Mans Rullgard (1):
>       omap4: l2x0: enable instruction and data prefetching
>
> Santosh Shilimkar (4):
>       ARM: l2x0: Add aux control register bitfields
>       omap4: l2x0: Construct the AUXCTRL value using defines
>       omap4: l2x0: Set share override bit
>       omap4: l2x0: Enable early BRESP bit
>
>  arch/arm/include/asm/hardware/cache-l2x0.h |   12 ++++++++++-
>  arch/arm/mach-omap2/omap4-common.c         |   30
+++++++++++++++++++++--
> ----
>  2 files changed, 34 insertions(+), 8 deletions(-)

[PATCH 0/5] omap4: l2x0 fixes and cleanup

[Santosh Shilimkar]

ping
> -----Original Message-----
> From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> Sent: Thursday, December 02, 2010 5:28 PM
> To: tony at atomide.com
> Cc: Nishanth Menon; mans at mansr.com; khilman at deeprootsystems.com; linux-
> arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org
> Subject: RE: [PATCH 0/5] omap4: l2x0 fixes and cleanup
>
> Tony,
> > -----Original Message-----
> > From: Santosh Shilimkar [mailto:santosh.shilimkar at ti.com]
> > Sent: Friday, November 19, 2010 11:01 PM
> > To: linux-omap at vger.kernel.org
> > Cc: nm at ti.com; mans at mansr.com; tony at atomide.com;
> > khilman at deeprootsystems.com; linux-arm-kernel at lists.infradead.org;
> Santosh
> > Shilimkar
> > Subject: [PATCH 0/5] omap4: l2x0 fixes and cleanup
> >
> > This series is outcome of the below discussion thread.
> > 	http://www.spinics.net/lists/arm-kernel/msg104254.html
> >
> > The series in brief has following patches
> > 	- adds PL310 aux-control register bitfields
> > 	- Use these bitfields instead of hardcoded values as part of init
> > 	- Enable PL310 intsruction, Data prefetch hints and  BRESP to
> > 		improve performance
> > 	- Set share-override bit to avoid non-cached buffer corruption
> >
> > Thanks to Nishant Menon for testing this series on OMAP4 panda using
> > the memspeed utility. Have boot tested this series on OMAP4 SDP with
> > omap2plus_defconfig.
> >
> How about merging this series in omap-testing if you are ok
> with it. Patch  " ARM: l2x0: Add aux control register bitfields"
> is already acked by Catalin.
>
> > The following changes since commit
> > e53beacd23d9cb47590da6a7a7f6d417b941a994:
> >   Linus Torvalds (1):
> >         Linux 2.6.37-rc2
> >
> > Mans Rullgard (1):
> >       omap4: l2x0: enable instruction and data prefetching
> >
> > Santosh Shilimkar (4):
> >       ARM: l2x0: Add aux control register bitfields
> >       omap4: l2x0: Construct the AUXCTRL value using defines
> >       omap4: l2x0: Set share override bit
> >       omap4: l2x0: Enable early BRESP bit
> >
> >  arch/arm/include/asm/hardware/cache-l2x0.h |   12 ++++++++++-
> >  arch/arm/mach-omap2/omap4-common.c         |   30
> +++++++++++++++++++++--
> > ----
> >  2 files changed, 34 insertions(+), 8 deletions(-)

[PATCH 0/5] omap4: l2x0 fixes and cleanup

[Tony Lindgren]

* Santosh Shilimkar <santosh.shilimkar@ti.com> [101213 21:08]:
> ping
...

> > How about merging this series in omap-testing if you are ok
> > with it. Patch  " ARM: l2x0: Add aux control register bitfields"
> > is already acked by Catalin.

Sorry for the delay on this series, applying.

Regards,

Tony