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Wed, 03 Jan 2024 10:32:31 -0800 (PST) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id j33-20020a635961000000b005c200b11b77sm22706829pgm.86.2024.01.03.10.32.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Jan 2024 10:32:29 -0800 (PST) Message-ID: Date: Wed, 3 Jan 2024 10:32:28 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: mm: Fix SOCs with DDR starting above zero To: Will Deacon , Elad Nachman Cc: catalin.marinas@arm.com, thunder.leizhen@huawei.com, bhe@redhat.com, akpm@linux-foundation.org, yajun.deng@linux.dev, chris.zjh@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20240103170002.1793197-1-enachman@marvell.com> <20240103174531.GE5954@willie-the-truck> From: Florian Fainelli Autocrypt: addr=florian.fainelli@broadcom.com; keydata= xsBNBFPAG8ABCAC3EO02urEwipgbUNJ1r6oI2Vr/+uE389lSEShN2PmL3MVnzhViSAtrYxeT M0Txqn1tOWoIc4QUl6Ggqf5KP6FoRkCrgMMTnUAINsINYXK+3OLe7HjP10h2jDRX4Ajs4Ghs JrZOBru6rH0YrgAhr6O5gG7NE1jhly+EsOa2MpwOiXO4DE/YKZGuVe6Bh87WqmILs9KvnNrQ PcycQnYKTVpqE95d4M824M5cuRB6D1GrYovCsjA9uxo22kPdOoQRAu5gBBn3AdtALFyQj9DQ KQuc39/i/Kt6XLZ/RsBc6qLs+p+JnEuPJngTSfWvzGjpx0nkwCMi4yBb+xk7Hki4kEslABEB AAHNMEZsb3JpYW4gRmFpbmVsbGkgPGZsb3JpYW4uZmFpbmVsbGlAYnJvYWRjb20uY29tPsLB IQQQAQgAyxcKAAG/SMv+fS3xUQWa0NryPuoRGjsA3SAUAAAAAAAWAAFrZXktdXNhZ2UtbWFz a0BwZ3AuY29tjDAUgAAAAAAgAAdwcmVmZXJyZWQtZW1haWwtZW5jb2RpbmdAcGdwLmNvbXBn cG1pbWUICwkIBwMCAQoFF4AAAAAZGGxkYXA6Ly9rZXlzLmJyb2FkY29tLmNvbQUbAwAAAAMW AgEFHgEAAAAEFQgJChYhBNXZKpfnkVze1+R8aIExtcQpvGagBQJk1oG9BQkj4mj6AAoJEIEx tcQpvGag13gH/2VKD6nojbJ9TBHLl+lFPIlOBZJ7UeNN8Cqhi9eOuH97r4Qw6pCnUOeoMlBH C6Dx8AcEU+OH4ToJ9LoaKIByWtK8nShayHqDc/vVoLasTwvivMAkdhhq6EpjG3WxDfOn8s5b Z/omGt/D/O8tg1gWqUziaBCX+JNvrV3aHVfbDKjk7KRfvhj74WMadtH1EOoVef0eB7Osb0GH 1nbrPZncuC4nqzuayPf0zbzDuV1HpCIiH692Rki4wo/72z7mMJPM9bNsUw1FTM4ALWlhdVgT gvolQPmfBPttY44KRBhR3Ipt8r/dMOlshaIW730PU9uoTkORrfGxreOUD3XT4g8omuvOwE0E U8AbwQEIAKxr71oqe+0+MYCc7WafWEcpQHFUwvYLcdBoOnmJPxDwDRpvU5LhqSPvk/yJdh9k 4xUDQu3rm1qIW2I9Puk5n/Jz/lZsqGw8T13DKyu8eMcvaA/irm9lX9El27DPHy/0qsxmxVmU pu9y9S+BmaMb2CM9IuyxMWEl9ruWFS2jAWh/R8CrdnL6+zLk60R7XGzmSJqF09vYNlJ6Bdbs MWDXkYWWP5Ub1ZJGNJQ4qT7g8IN0qXxzLQsmz6tbgLMEHYBGx80bBF8AkdThd6SLhreCN7Uh IR/5NXGqotAZao2xlDpJLuOMQtoH9WVNuuxQQZHVd8if+yp6yRJ5DAmIUt5CCPcAEQEAAcLB gQQYAQIBKwUCU8AbwgUbDAAAAMBdIAQZAQgABgUCU8AbwQAKCRCTYAaomC8PVQ0VCACWk3n+ obFABEp5Rg6Qvspi9kWXcwCcfZV41OIYWhXMoc57ssjCand5noZi8bKg0bxw4qsg+9cNgZ3P N/DFWcNKcAT3Z2/4fTnJqdJS//YcEhlr8uGs+ZWFcqAPbteFCM4dGDRruo69IrHfyyQGx16s CcFlrN8vD066RKevFepb/ml7eYEdN5SRALyEdQMKeCSf3mectdoECEqdF/MWpfWIYQ1hEfdm C2Kztm+h3Nkt9ZQLqc3wsPJZmbD9T0c9Rphfypgw/SfTf2/CHoYVkKqwUIzI59itl5Lze+R5 wDByhWHx2Ud2R7SudmT9XK1e0x7W7a5z11Q6vrzuED5nQvkhAAoJEIExtcQpvGagugcIAJd5 EYe6KM6Y6RvI6TvHp+QgbU5dxvjqSiSvam0Ms3QrLidCtantcGT2Wz/2PlbZqkoJxMQc40rb fXa4xQSvJYj0GWpadrDJUvUu3LEsunDCxdWrmbmwGRKqZraV2oG7YEddmDqOe0Xm/NxeSobc MIlnaE6V0U8f5zNHB7Y46yJjjYT/Ds1TJo3pvwevDWPvv6rdBeV07D9s43frUS6xYd1uFxHC 7dZYWJjZmyUf5evr1W1gCgwLXG0PEi9n3qmz1lelQ8lSocmvxBKtMbX/OKhAfuP/iIwnTsww 95A2SaPiQZA51NywV8OFgsN0ITl2PlZ4Tp9hHERDe6nQCsNI/Us= In-Reply-To: <20240103174531.GE5954@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240103_103235_188145_82CDED30 X-CRM114-Status: GOOD ( 24.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============2224362402397817560==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============2224362402397817560== Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="00000000000082c360060e0ed63a" --00000000000082c360060e0ed63a Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/3/24 09:45, Will Deacon wrote: > On Wed, Jan 03, 2024 at 07:00:02PM +0200, Elad Nachman wrote: >> From: Elad Nachman >> >> Some SOCs, like the Marvell AC5/X/IM, have a combination >> of DDR starting at 0x2_0000_0000 coupled with DMA controllers >> limited to 31 and 32 bit of addressing. >> This requires to properly arrange ZONE_DMA and ZONE_DMA32 for >> these SOCs, so swiotlb and coherent DMA allocation would work >> properly. >> Change initialization so device tree dma zone bits are taken as >> function of offset from DRAM start, and when calculating the >> maximal zone physical RAM address for physical DDR starting above >> 32-bit, combine the physical address start plus the zone mask >> passed as parameter. >> This creates the proper zone splitting for these SOCs: >> 0..2GB for ZONE_DMA >> 2GB..4GB for ZONE_DMA32 >> 4GB..8GB for ZONE_NORMAL >> >> Signed-off-by: Elad Nachman >> --- >> arch/arm64/mm/init.c | 20 +++++++++++++++----- >> 1 file changed, 15 insertions(+), 5 deletions(-) >> >> diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c >> index 74c1db8ce271..8288c778916e 100644 >> --- a/arch/arm64/mm/init.c >> +++ b/arch/arm64/mm/init.c >> @@ -115,20 +115,21 @@ static void __init arch_reserve_crashkernel(void) >> >> /* >> * Return the maximum physical address for a zone accessible by the given bits >> - * limit. If DRAM starts above 32-bit, expand the zone to the maximum >> - * available memory, otherwise cap it at 32-bit. >> + * limit. If DRAM starts above 32-bit, expand the zone to the available memory >> + * start limited by the zone bits mask, otherwise cap it at 32-bit. >> */ >> static phys_addr_t __init max_zone_phys(unsigned int zone_bits) >> { >> phys_addr_t zone_mask = DMA_BIT_MASK(zone_bits); >> phys_addr_t phys_start = memblock_start_of_DRAM(); >> + phys_addr_t phys_end = memblock_end_of_DRAM(); >> >> if (phys_start > U32_MAX) >> - zone_mask = PHYS_ADDR_MAX; >> + zone_mask = phys_start | zone_mask; >> else if (phys_start > zone_mask) >> zone_mask = U32_MAX; >> >> - return min(zone_mask, memblock_end_of_DRAM() - 1) + 1; >> + return min(zone_mask, phys_end - 1) + 1; >> } >> >> static void __init zone_sizes_init(void) >> @@ -140,7 +141,16 @@ static void __init zone_sizes_init(void) >> >> #ifdef CONFIG_ZONE_DMA >> acpi_zone_dma_bits = fls64(acpi_iort_dma_get_max_cpu_address()); >> - dt_zone_dma_bits = fls64(of_dma_get_max_cpu_address(NULL)); >> + /* >> + * When calculating the dma zone bits from the device tree, subtract >> + * the DRAM start address, in case it does not start from address >> + * zero. This way. we pass only the zone size related bits to >> + * max_zone_phys(), which will add them to the base of the DRAM. >> + * This prevents miscalculations on arm64 SOCs which combines >> + * DDR starting above 4GB with memory controllers limited to >> + * 32-bits or less: >> + */ >> + dt_zone_dma_bits = fls64(of_dma_get_max_cpu_address(NULL) - memblock_start_of_DRAM()); >> zone_dma_bits = min3(32U, dt_zone_dma_bits, acpi_zone_dma_bits); >> arm64_dma_phys_limit = max_zone_phys(zone_dma_bits); >> max_zone_pfns[ZONE_DMA] = PFN_DOWN(arm64_dma_phys_limit); > > Hmm, I'm a bit worried this could regress other platforms since you seem > to be assuming that DMA address 0 corresponds to the physical start of > DRAM. What if that isn't the case? All of our most recent Set-top-box SoCs map DRAM starting at PA 0x4000_0000 FWIW. We have the following memory maps: 1. DRAM mapped at PA 0x0000_0000 2. DRAM mapped at PA 0x4000_0000 with another memory controller starting at 0x3_0000_0000 3. DRAM mapped at PA 0x4000_0000 with a single memory controller. Here is the before/after diff with debugging prints introduced to print start, end, min, mask and the dt_zone_dma_bits value: Memory map 1. with 2GB -> no change in output Memory map 2. with 2+2GB -> no change in output Memory map 3. with 4GB: @@ -39,7 +39,7 @@ [ 0.000000] OF: reserved mem: 0x00000000fdfff000..0x00000000fdffffff (4 KiB) nomap non-reusable NWMBOX [ 0.000000] OF: reserved mem: 0x00000000fe000000..0x00000000ffffffff (32768 KiB) nomap non-reusable SRR@fe000000 [ 0.000000] max_zone_phys: start: 0x0000000040000000, end: 0x0000000140000000, min: 0x0000000100000000, mask: 0x00000000ffffffff -[ 0.000000] zone_sizes_init: dt_zone_dma_bits: 0x00000021 +[ 0.000000] zone_sizes_init: dt_zone_dma_bits: 0x00000020 [ 0.000000] max_zone_phys: start: 0x0000000040000000, end: 0x0000000140000000, min: 0x0000000100000000, mask: 0x00000000ffffffff [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff] @@ -88,243 +88,243 @@ Memory map 3. with 2GB: @@ -39,11 +39,11 @@ [ 0.000000] OF: reserved mem: 0x00000000bdfff000..0x00000000bdffffff (4 KiB) nomap non-reusable NWMBOX [ 0.000000] OF: reserved mem: 0x00000000be000000..0x00000000bfffffff (32768 KiB) nomap non-reusable SRR@be000000 [ 0.000000] max_zone_phys: start: 0x0000000040000000, end: 0x00000000c0000000, min: 0x00000000c0000000, mask: 0x00000000ffffffff -[ 0.000000] zone_sizes_init: dt_zone_dma_bits: 0x00000020 -[ 0.000000] max_zone_phys: start: 0x0000000040000000, end: 0x00000000c0000000, min: 0x00000000c0000000, mask: 0x00000000ffffffff +[ 0.000000] zone_sizes_init: dt_zone_dma_bits: 0x0000001f +[ 0.000000] max_zone_phys: start: 0x0000000040000000, end: 0x00000000c0000000, min: 0x0000000080000000, mask: 0x000000007fffffff [ 0.000000] Zone ranges: -[ 0.000000] DMA [mem 0x0000000040000000-0x00000000bfffffff] -[ 0.000000] DMA32 empty +[ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff] +[ 0.000000] DMA32 [mem 0x0000000080000000-0x00000000bfffffff] [ 0.000000] Normal empty [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges @@ -54,7 +54,7 @@ -- Florian --00000000000082c360060e0ed63a Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQeQYJKoZIhvcNAQcCoIIQajCCEGYCAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg gg3QMIIFDTCCA/WgAwIBAgIQeEqpED+lv77edQixNJMdADANBgkqhkiG9w0BAQsFADBMMSAwHgYD VQQLExdHbG9iYWxTaWduIFJvb3QgQ0EgLSBSMzETMBEGA1UEChMKR2xvYmFsU2lnbjETMBEGA1UE AxMKR2xvYmFsU2lnbjAeFw0yMDA5MTYwMDAwMDBaFw0yODA5MTYwMDAwMDBaMFsxCzAJBgNVBAYT AkJFMRkwFwYDVQQKExBHbG9iYWxTaWduIG52LXNhMTEwLwYDVQQDEyhHbG9iYWxTaWduIEdDQyBS MyBQZXJzb25hbFNpZ24gMiBDQSAyMDIwMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA vbCmXCcsbZ/a0fRIQMBxp4gJnnyeneFYpEtNydrZZ+GeKSMdHiDgXD1UnRSIudKo+moQ6YlCOu4t rVWO/EiXfYnK7zeop26ry1RpKtogB7/O115zultAz64ydQYLe+a1e/czkALg3sgTcOOcFZTXk38e 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