* [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals
@ 2025-05-12 12:05 Linus Walleij
2025-05-12 12:05 ` [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number Linus Walleij
` (11 more replies)
0 siblings, 12 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij,
Krzysztof Kozlowski
This adds a bunch peripherals to the Broadcom BRCMBCA
SoC:s that I happened to find documentation for in some
vendor header files.
It started when I added a bunch of peripherals for the
BCM6846, and this included really helpful peripherals
such as the PL081 DMA, for which I think the most common
usecase is to be used as a memcpy engine to offload
transfer of blocks from NAND flash to/from the NAND
flash controller (at least this is how the STMicro
FSMC controller was using it).
So I took a sweep and added all the stuff that has
bindings to:
ARM:
- BCM6846
- BCM6855
- BCM6878
- BCM63138
- BCM63148
- BCM63178
ARM64:
- BCM4908
- BCM6856
- BCM6858
- BCM63158
There are several "holes" in this SoC list, I simply
just fixed those that I happened to run into documentation
for.
Unfortunately while very similar, some IP blocks vary
slightly in version, the GPIO block is differently
integrated on different systems, and the interrupt assignments
are completely different, so it's safest to add these to each
DTSI individually.
I add the interrupt binding for the RNG block in the
process as this exists even if Linux isn't using the
IRQ, and I put the RNG and DMA engines as default-enabled
because they are not routed to the outside and should
"just work" so why not.
I did a rogue patch adding some stuff to BCM6756 based
on guessed but eventually dropped it. If someone has
docs for this SoC I can add it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Changes in v3:
- Rebased in v6.15-rc1
- Set the UART IRQ to 92 and not 28 on BCM6878.
- Set RNG IRQ to 85 on BCM6878
- Set RNG IRQ to 85 on BCM6846.
- Set RNG IRQ to 85 on BCM63138.
- Extend the peripheral bus to 0x400000 on the BCM4908 and
add the DMA at offset 0x59000.
- Extend the peripheral bus to 0x400000 on the BCM6856 and
add the DMA at offset 0x59000.
- Extend the peripheral bus to 0x400000 on the BCM6858 and
add the DMA at offset 0x59000.
- Use the existing 0x800000 peripheral window for the extra
peripherals on the BCM63158 instead of defining subwindows.
- Link to v2: https://lore.kernel.org/r/20250406-bcmbca-peripherals-arm-v2-0-22130836c2ed@linaro.org
Changes in v2:
- Pick up Krzysztof's ACK
- Push the BCM6858 DMA block into its own simple bus.
- Fix GPIO node names and registers on BCM63138.
- Fix GPIO node names and registers on BCM63148.
- Link to v1: https://lore.kernel.org/r/20250328-bcmbca-peripherals-arm-v1-0-e4e515dc9b8c@linaro.org
---
Linus Walleij (12):
ARM: dts: bcm6878: Correct UART0 IRQ number
dt-bindings: rng: r200: Add interrupt property
ARM: dts: bcm6846: Add interrupt to RNG
ARM: dts: bcm6855: Add BCMBCA peripherals
ARM: dts: bcm6878: Add BCMBCA peripherals
ARM: dts: bcm63138: Add BCMBCA peripherals
ARM: dts: bcm63148: Add BCMBCA peripherals
ARM: dts: bcm63178: Add BCMBCA peripherals
ARM64: dts: bcm4908: Add BCMBCA peripherals
ARM64: dts: bcm6856: Add BCMBCA peripherals
ARM64: dts: bcm6858: Add BCMBCA peripherals
ARM64: dts: bcm63158: Add BCMBCA peripherals
.../devicetree/bindings/rng/brcm,iproc-rng200.yaml | 6 +
arch/arm/boot/dts/broadcom/bcm63138.dtsi | 79 ++++++++++++-
arch/arm/boot/dts/broadcom/bcm63148.dtsi | 64 ++++++++++
arch/arm/boot/dts/broadcom/bcm63178.dtsi | 112 ++++++++++++++++++
arch/arm/boot/dts/broadcom/bcm6846.dtsi | 1 +
arch/arm/boot/dts/broadcom/bcm6855.dtsi | 127 ++++++++++++++++++++
arch/arm/boot/dts/broadcom/bcm6878.dtsi | 120 ++++++++++++++++++-
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 116 +++++++++++++++++-
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 129 ++++++++++++++++++++
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 130 ++++++++++++++++++++-
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 119 ++++++++++++++++++-
11 files changed, 996 insertions(+), 7 deletions(-)
---
base-commit: 35ec8841914c9777209046ea0838acbe23e06b39
change-id: 20250327-bcmbca-peripherals-arm-dfb312052363
Best regards,
--
Linus Walleij <linus.walleij@linaro.org>
^ permalink raw reply [flat|nested] 36+ messages in thread
* [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:33 ` William Zhang
2025-05-13 8:52 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 02/12] dt-bindings: rng: r200: Add interrupt property Linus Walleij
` (10 subsequent siblings)
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
According to the vendor file 6878_intr.h the UART0 has IRQ
92, not 32.
Assuming this is a copy-and-paste error.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/broadcom/bcm6878.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
index 70cf23a65fdb5ac7ed9eabc986f4ebb4df263c43..43eb678e14d04be487af39c9365186b6fb919cf3 100644
--- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
@@ -137,7 +137,7 @@ nandcs: nand@0 {
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>, <&uart_clk>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 02/12] dt-bindings: rng: r200: Add interrupt property
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
2025-05-12 12:05 ` [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-13 8:52 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG Linus Walleij
` (9 subsequent siblings)
11 siblings, 1 reply; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij,
Krzysztof Kozlowski
This IP block has an interrupt. Add it and add it to the
example as well.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml
index 827983008ecf707019f45847cd86d5686e3b2469..817cbdaa2b2d75705eda212521186c40a9975ea0 100644
--- a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml
+++ b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml
@@ -20,11 +20,17 @@ properties:
reg:
maxItems: 1
+ interrupts:
+ maxItems: 1
+
additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
rng@18032000 {
compatible = "brcm,iproc-rng200";
reg = <0x18032000 0x28>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
2025-05-12 12:05 ` [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number Linus Walleij
2025-05-12 12:05 ` [PATCH v3 02/12] dt-bindings: rng: r200: Add interrupt property Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:34 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals Linus Walleij
` (8 subsequent siblings)
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
The r200 RNG has an interrupt so let's add it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/broadcom/bcm6846.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/broadcom/bcm6846.dtsi b/arch/arm/boot/dts/broadcom/bcm6846.dtsi
index e0e06af3fe891df3c3d8c2005cf1980d33a7762b..f5591a45d2e4ad64d8f95680aea327771825252b 100644
--- a/arch/arm/boot/dts/broadcom/bcm6846.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi
@@ -196,6 +196,7 @@ uart0: serial@640 {
rng@b80 {
compatible = "brcm,iproc-rng200";
reg = <0xb80 0x28>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
};
leds: led-controller@800 {
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
` (2 preceding siblings ...)
2025-05-12 12:05 ` [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:35 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 05/12] ARM: dts: bcm6878: " Linus Walleij
` (7 subsequent siblings)
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments.
Add the first and second watchdog, GPIO, RNG, LED, DMA and
second PL011 UART blocks for the BCM6855 based on the vendor
files 6855_map_part.h and 6855_intr.h from the
"bcmopen-consumer" code drop.
This SoC has up to 256 possible GPIOs due to having 8
registers with 32 GPIOs in each available.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/broadcom/bcm6855.dtsi | 127 ++++++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/arch/arm/boot/dts/broadcom/bcm6855.dtsi b/arch/arm/boot/dts/broadcom/bcm6855.dtsi
index 52915ec6f339335d87b4e50e1c03625fffb9a45d..a88c3f0fbcb037ee5c6b31933415f90cb51ded2a 100644
--- a/arch/arm/boot/dts/broadcom/bcm6855.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6855.dtsi
@@ -116,6 +116,103 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
+ watchdog@480 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x480 0x10>;
+ };
+
+ watchdog@4c0 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x4c0 0x10>;
+ status = "disabled";
+ };
+
+ /* GPIOs 0 .. 31 */
+ gpio0: gpio@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x500 0x04>, <0x520 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 32 .. 63 */
+ gpio1: gpio@504 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x504 0x04>, <0x524 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 64 .. 95 */
+ gpio2: gpio@508 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x508 0x04>, <0x528 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 96 .. 127 */
+ gpio3: gpio@50c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x50c 0x04>, <0x52c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 128 .. 159 */
+ gpio4: gpio@510 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x510 0x04>, <0x530 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 160 .. 191 */
+ gpio5: gpio@514 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x514 0x04>, <0x534 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 192 .. 223 */
+ gpio6: gpio@518 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x518 0x04>, <0x538 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 224 .. 255 */
+ gpio7: gpio@51c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x51c 0x04>, <0x53c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rng@b80 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0xb80 0x28>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -143,6 +240,27 @@ nandcs: nand@0 {
};
};
+ leds: led-controller@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-leds";
+ reg = <0x3000 0xdc>;
+ status = "disabled";
+ };
+
+ pl081_dma: dma-controller@11000 {
+ compatible = "arm,pl081", "arm,primecell";
+ // The magic B105F00D info is missing
+ arm,primecell-periphid = <0x00041081>;
+ reg = <0x11000 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ clocks = <&periph_clk>;
+ clock-names = "apb_pclk";
+ #dma-cells = <2>;
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
@@ -151,5 +269,14 @@ uart0: serial@12000 {
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ uart1: serial@13000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x13000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
};
};
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 05/12] ARM: dts: bcm6878: Add BCMBCA peripherals
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
` (3 preceding siblings ...)
2025-05-12 12:05 ` [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:37 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 06/12] ARM: dts: bcm63138: " Linus Walleij
` (6 subsequent siblings)
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments.
Add the first and second watchdog, GPIO, RNG, LED and
DMA blocks for the BCM6878 based on the vendor files
6878_map_part.h and 6878_intr.h from the "bcmopen-consumer"
code drop.
This SoC has up to 256 possible GPIOs due to having 8
registers with 32 GPIOs in each available.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/broadcom/bcm6878.dtsi | 118 ++++++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
index 43eb678e14d04be487af39c9365186b6fb919cf3..dd837bf693905736a7b8ef9cfefea8368e6df6ed 100644
--- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
@@ -108,6 +108,111 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
+ watchdog@480 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x480 0x10>;
+ };
+
+ watchdog@4c0 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x4c0 0x10>;
+ status = "disabled";
+ };
+
+ /* GPIOs 0 .. 31 */
+ gpio0: gpio@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x500 0x04>, <0x520 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 32 .. 63 */
+ gpio1: gpio@504 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x504 0x04>, <0x524 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 64 .. 95 */
+ gpio2: gpio@508 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x508 0x04>, <0x528 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 96 .. 127 */
+ gpio3: gpio@50c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x50c 0x04>, <0x52c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 128 .. 159 */
+ gpio4: gpio@510 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x510 0x04>, <0x530 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 160 .. 191 */
+ gpio5: gpio@514 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x514 0x04>, <0x534 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 192 .. 223 */
+ gpio6: gpio@518 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x518 0x04>, <0x538 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 224 .. 255 */
+ gpio7: gpio@51c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x51c 0x04>, <0x53c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rng@b80 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0xb80 0x28>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ leds: led-controller@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-leds";
+ reg = <0x700 0xdc>;
+ status = "disabled";
+ };
+
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -134,6 +239,19 @@ nandcs: nand@0 {
};
};
+ pl081_dma: dma-controller@11000 {
+ compatible = "arm,pl081", "arm,primecell";
+ // The magic B105F00D info is missing
+ arm,primecell-periphid = <0x00041081>;
+ reg = <0x11000 0x1000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ clocks = <&periph_clk>;
+ clock-names = "apb_pclk";
+ #dma-cells = <2>;
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 06/12] ARM: dts: bcm63138: Add BCMBCA peripherals
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
` (4 preceding siblings ...)
2025-05-12 12:05 ` [PATCH v3 05/12] ARM: dts: bcm6878: " Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:38 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 07/12] ARM: dts: bcm63148: " Linus Walleij
` (5 subsequent siblings)
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments.
Extend the peripheral interrupt window to 0x10000 as it need
to fit the DMA block.
Add the GPIO, RNG and LED and DMA blocks for the
BCM63138 based on the vendor files 63138_map_part.h and
63138_intr.h from the "bcmopen-consumer" code drop.
This SoC has up to 160 possible GPIOs due to having 5
registers with 32 GPIOs in each available.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/broadcom/bcm63138.dtsi | 79 +++++++++++++++++++++++++++++++-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/broadcom/bcm63138.dtsi b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
index e74ba6bf370da63d3c115e38b4f20c71baff2116..4ec568586b14c89daceddea8f17381f72f512a93 100644
--- a/arch/arm/boot/dts/broadcom/bcm63138.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
@@ -184,13 +184,69 @@ ubus@fffe8000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0 0xfffe8000 0x8100>;
+ ranges = <0 0xfffe8000 0x10000>;
timer: timer@80 {
compatible = "brcm,bcm6328-timer", "syscon";
reg = <0x80 0x3c>;
};
+ /* GPIOs 0 .. 31 */
+ gpio0: gpio@100 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x100 0x04>, <0x114 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 32 .. 63 */
+ gpio1: gpio@104 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x104 0x04>, <0x118 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 64 .. 95 */
+ gpio2: gpio@108 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x108 0x04>, <0x11c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 96 .. 127 */
+ gpio3: gpio@10c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x10c 0x04>, <0x120 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 128 .. 159 */
+ gpio4: gpio@110 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x110 0x04>, <0x124 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rng@300 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0x300 0x28>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
serial0: serial@600 {
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x1b>;
@@ -209,6 +265,14 @@ serial1: serial@620 {
status = "disabled";
};
+ leds: led-controller@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-leds";
+ reg = <0x700 0xdc>;
+ status = "disabled";
+ };
+
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -248,6 +312,19 @@ bootlut: bootlut@8000 {
reg = <0x8000 0x50>;
};
+ pl081_dma: dma-controller@d000 {
+ compatible = "arm,pl081", "arm,primecell";
+ // The magic B105F00D info is missing
+ arm,primecell-periphid = <0x00041081>;
+ reg = <0xd000 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ clocks = <&periph_clk>;
+ clock-names = "apb_pclk";
+ #dma-cells = <2>;
+ };
+
reboot {
compatible = "syscon-reboot";
regmap = <&timer>;
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 07/12] ARM: dts: bcm63148: Add BCMBCA peripherals
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
` (5 preceding siblings ...)
2025-05-12 12:05 ` [PATCH v3 06/12] ARM: dts: bcm63138: " Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:38 ` William Zhang
2025-05-13 8:56 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 08/12] ARM: dts: bcm63178: " Linus Walleij
` (4 subsequent siblings)
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments.
Add the GPIO, RNG and LED and DMA blocks for the
BCM63148 based on the vendor files 63148_map_part.h and
63148_intr.h from the "bcmopen-consumer" code drop.
This SoC has up to 160 possible GPIOs due to having 5
registers with 32 GPIOs in each available.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/broadcom/bcm63148.dtsi | 64 ++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm/boot/dts/broadcom/bcm63148.dtsi b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
index 53703827ee3fe58ead1dbe70536d7293ad842d0c..e071cddb28fc2888b8f408b4bc275290dd135642 100644
--- a/arch/arm/boot/dts/broadcom/bcm63148.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
@@ -99,6 +99,62 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0 0xfffe8000 0x8000>;
+ /* GPIOs 0 .. 31 */
+ gpio0: gpio@100 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x100 0x04>, <0x114 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 32 .. 63 */
+ gpio1: gpio@104 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x104 0x04>, <0x118 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 64 .. 95 */
+ gpio2: gpio@108 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x108 0x04>, <0x11c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 96 .. 127 */
+ gpio3: gpio@10c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x10c 0x04>, <0x120 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 128 .. 159 */
+ gpio4: gpio@110 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x110 0x04>, <0x124 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rng@300 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0x300 0x28>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
uart0: serial@600 {
compatible = "brcm,bcm6345-uart";
reg = <0x600 0x20>;
@@ -108,6 +164,14 @@ uart0: serial@600 {
status = "disabled";
};
+ leds: led-controller@700 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-leds";
+ reg = <0x700 0xdc>;
+ status = "disabled";
+ };
+
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 08/12] ARM: dts: bcm63178: Add BCMBCA peripherals
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
` (6 preceding siblings ...)
2025-05-12 12:05 ` [PATCH v3 07/12] ARM: dts: bcm63148: " Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:39 ` William Zhang
2025-05-13 8:57 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 09/12] ARM64: dts: bcm4908: " Linus Walleij
` (3 subsequent siblings)
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments.
Add the watchdog, GPIO, RNG, LED and DMA blocks for the
BCM63178 based on the vendor files 63178_map_part.h and
63178_intr.h from the "bcmopen-consumer" code drop.
This SoC has up to 256 possible GPIOs due to having 8
registers with 32 GPIOs in each available.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/broadcom/bcm63178.dtsi | 112 +++++++++++++++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/arch/arm/boot/dts/broadcom/bcm63178.dtsi b/arch/arm/boot/dts/broadcom/bcm63178.dtsi
index 6d8d33498983acfc0c65ee155f64ddedc4a6b376..430750b3030f2534d6bf0468d895ca565007a53f 100644
--- a/arch/arm/boot/dts/broadcom/bcm63178.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm63178.dtsi
@@ -117,6 +117,97 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0 0xff800000 0x800000>;
+ watchdog@480 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x480 0x10>;
+ };
+
+ /* GPIOs 0 .. 31 */
+ gpio0: gpio@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x500 0x04>, <0x520 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 32 .. 63 */
+ gpio1: gpio@504 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x504 0x04>, <0x524 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 64 .. 95 */
+ gpio2: gpio@508 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x508 0x04>, <0x528 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 96 .. 127 */
+ gpio3: gpio@50c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x50c 0x04>, <0x52c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 128 .. 159 */
+ gpio4: gpio@510 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x510 0x04>, <0x530 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 160 .. 191 */
+ gpio5: gpio@514 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x514 0x04>, <0x534 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 192 .. 223 */
+ gpio6: gpio@518 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x518 0x04>, <0x538 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 224 .. 255 */
+ gpio7: gpio@51c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x51c 0x04>, <0x53c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rng@b80 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0xb80 0x28>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -143,6 +234,27 @@ nandcs: nand@0 {
};
};
+ leds: led-controller@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-leds";
+ reg = <0x3000 0xdc>;
+ status = "disabled";
+ };
+
+ pl081_dma: dma-controller@11000 {
+ compatible = "arm,pl081", "arm,primecell";
+ // The magic B105F00D info is missing
+ arm,primecell-periphid = <0x00041081>;
+ reg = <0x11000 0x1000>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ clocks = <&periph_clk>;
+ clock-names = "apb_pclk";
+ #dma-cells = <2>;
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 09/12] ARM64: dts: bcm4908: Add BCMBCA peripherals
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
` (7 preceding siblings ...)
2025-05-12 12:05 ` [PATCH v3 08/12] ARM: dts: bcm63178: " Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:42 ` William Zhang
2025-05-13 8:57 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 10/12] ARM64: dts: bcm6856: " Linus Walleij
` (2 subsequent siblings)
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments. ARM64 SoCs have additional
peripherals at 0xff858000, we extend the peripheral bus
range to 0x400000 to cover this area.
Add the watchdog, remaining GPIO blocks, RNG, and DMA blocks
for the BCM4908 based on the vendor files 4908_map_part.h
and 4908_intr.h from the "bcmopen-consumer" code drop.
This SoC has up to 320 possible GPIOs due to having 10
registers with 32 GPIOs in each available.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 116 ++++++++++++++++++++++-
1 file changed, 113 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
index 613ba7ee43d6489ea0f1490d2fccaf90961b2694..3b7595fd4e81d150278816bbe27e08286cde2ff8 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
@@ -323,11 +323,12 @@ pmb: power-controller@2800c0 {
};
};
+ /* PERF Peripherals */
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x00 0x00 0xff800000 0x3000>;
+ ranges = <0x00 0x00 0xff800000 0x400000>;
twd: timer-mfd@400 {
compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
@@ -348,13 +349,103 @@ watchdog@28 {
};
};
- gpio0: gpio-controller@500 {
+ /* GPIOs 0 .. 31 */
+ gpio0: gpio@500 {
compatible = "brcm,bcm6345-gpio";
+ reg = <0x500 0x04>, <0x528 0x04>;
reg-names = "dirout", "dat";
- reg = <0x500 0x28>, <0x528 0x28>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ /* GPIOs 32 .. 63 */
+ gpio1: gpio@504 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x504 0x04>, <0x52c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 64 .. 95 */
+ gpio2: gpio@508 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x508 0x04>, <0x530 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+ /* GPIOs 96 .. 127 */
+ gpio3: gpio@50c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x50c 0x04>, <0x534 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
#gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 128 .. 159 */
+ gpio4: gpio@510 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x510 0x04>, <0x538 0x04>;
+ reg-names = "dirout", "dat";
gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 160 .. 191 */
+ gpio5: gpio@514 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x514 0x04>, <0x53c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 192 .. 223 */
+ gpio6: gpio@518 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x518 0x04>, <0x540 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 224 .. 255 */
+ gpio7: gpio@51c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x51c 0x04>, <0x544 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 256 .. 287 */
+ gpio8: gpio@520 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x520 0x04>, <0x548 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 288 .. 319 */
+ gpio9: gpio@524 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x524 0x04>, <0x54c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
};
pinctrl@560 {
@@ -584,6 +675,12 @@ leds: leds@800 {
#size-cells = <0>;
};
+ rng@b80 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0xb80 0x28>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -636,6 +733,19 @@ reset-controller@2644 {
#reset-cells = <1>;
};
};
+
+ pl081_dma: dma-controller@59000 {
+ compatible = "arm,pl081", "arm,primecell";
+ // The magic B105F00D info is missing
+ arm,primecell-periphid = <0x00041081>;
+ reg = <0x59000 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ clocks = <&periph_clk>;
+ clock-names = "apb_pclk";
+ #dma-cells = <2>;
+ };
};
reboot {
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 10/12] ARM64: dts: bcm6856: Add BCMBCA peripherals
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
` (8 preceding siblings ...)
2025-05-12 12:05 ` [PATCH v3 09/12] ARM64: dts: bcm4908: " Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:43 ` William Zhang
2025-05-13 8:58 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 11/12] ARM64: dts: bcm6858: " Linus Walleij
2025-05-12 12:05 ` [PATCH v3 12/12] ARM64: dts: bcm63158: " Linus Walleij
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments. ARM64 SoCs have additional
peripherals at 0xff858000. Extend the BCM6856 the PERF window
to 0x400000 and add the DMA block at offset 0x59000.
Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA
blocks for the BCM6856 based on the vendor files 6856_map_part.h
and 6856_intr.h from the "bcmopen-consumer" code drop.
This SoC has up to 256 possible GPIOs due to having 8
registers with 32 GPIOs in each available.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 130 ++++++++++++++++++++++-
1 file changed, 129 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
index 00c62c1e5df00c722884a7adfcb7be08a43c0dc3..dcbd0fdd33d25fa340c417e8284826801ebc00bb 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
@@ -93,11 +93,103 @@ gic: interrupt-controller@1000 {
};
};
+ /* PERF Peripherals */
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x800000>;
+ ranges = <0x0 0x0 0xff800000 0x400000>;
+
+ watchdog@480 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x480 0x10>;
+ };
+
+ watchdog@4c0 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x4c0 0x10>;
+ status = "disabled";
+ };
+
+ /* GPIOs 0 .. 31 */
+ gpio0: gpio@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x500 0x04>, <0x520 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 32 .. 63 */
+ gpio1: gpio@504 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x504 0x04>, <0x524 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 64 .. 95 */
+ gpio2: gpio@508 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x508 0x04>, <0x528 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 96 .. 127 */
+ gpio3: gpio@50c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x50c 0x04>, <0x52c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 128 .. 159 */
+ gpio4: gpio@510 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x510 0x04>, <0x530 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 160 .. 191 */
+ gpio5: gpio@514 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x514 0x04>, <0x534 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 192 .. 223 */
+ gpio6: gpio@518 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x518 0x04>, <0x538 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 224 .. 255 */
+ gpio7: gpio@51c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x51c 0x04>, <0x53c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
@@ -108,6 +200,29 @@ uart0: serial@640 {
status = "disabled";
};
+ uart1: serial@660 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x660 0x18>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+
+ leds: led-controller@800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-leds";
+ reg = <0x800 0xdc>;
+ status = "disabled";
+ };
+
+ rng@b80 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0xb80 0x28>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -133,5 +248,18 @@ nandcs: nand@0 {
reg = <0>;
};
};
+
+ pl081_dma: dma-controller@59000 {
+ compatible = "arm,pl081", "arm,primecell";
+ // The magic B105F00D info is missing
+ arm,primecell-periphid = <0x00041081>;
+ reg = <0x59000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ clocks = <&periph_clk>;
+ clock-names = "apb_pclk";
+ #dma-cells = <2>;
+ };
};
};
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 11/12] ARM64: dts: bcm6858: Add BCMBCA peripherals
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
` (9 preceding siblings ...)
2025-05-12 12:05 ` [PATCH v3 10/12] ARM64: dts: bcm6856: " Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:44 ` William Zhang
2025-05-13 8:58 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 12/12] ARM64: dts: bcm63158: " Linus Walleij
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments. ARM64 SoCs have additional
peripherals at 0xff858000. Extend the peripheral window range
to 0x400000 and add the DMA controller at offset 0x59000.
Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA
blocks for the BCM6858 based on the vendor files 6858_map_part.h
and 6858_intr.h from the "bcmopen-consumer" code drop.
This SoC has up to 256 possible GPIOs due to having 8
registers with 32 GPIOs in each available.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 119 ++++++++++++++++++++++-
1 file changed, 118 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
index caeaf428dc15db3089bf4dc62c4a272782c22c3f..c105a734a64897e714ed107e0ddccc5eebd415da 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
@@ -111,11 +111,12 @@ gic: interrupt-controller@1000 {
};
};
+ /* PERF Peripherals */
bus@ff800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x62000>;
+ ranges = <0x0 0x0 0xff800000 0x400000>;
twd: timer-mfd@400 {
compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
@@ -136,6 +137,86 @@ watchdog@28 {
};
};
+ /* GPIOs 0 .. 31 */
+ gpio0: gpio@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x500 0x04>, <0x520 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 32 .. 63 */
+ gpio1: gpio@504 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x504 0x04>, <0x524 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 64 .. 95 */
+ gpio2: gpio@508 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x508 0x04>, <0x528 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 96 .. 127 */
+ gpio3: gpio@50c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x50c 0x04>, <0x52c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 128 .. 159 */
+ gpio4: gpio@510 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x510 0x04>, <0x530 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 160 .. 191 */
+ gpio5: gpio@514 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x514 0x04>, <0x534 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 192 .. 223 */
+ gpio6: gpio@518 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x518 0x04>, <0x538 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 224 .. 255 */
+ gpio7: gpio@51c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x51c 0x04>, <0x53c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
reg = <0x640 0x18>;
@@ -145,6 +226,29 @@ uart0: serial@640 {
status = "disabled";
};
+ uart1: serial@660 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x660 0x18>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+
+ leds: led-controller@800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-leds";
+ reg = <0x800 0xdc>;
+ status = "disabled";
+ };
+
+ rng@b80 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0xb80 0x28>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -170,5 +274,18 @@ nandcs: nand@0 {
reg = <0>;
};
};
+
+ pl081_dma: dma-controller@59000 {
+ compatible = "arm,pl081", "arm,primecell";
+ // The magic B105F00D info is missing
+ arm,primecell-periphid = <0x00041081>;
+ reg = <0x59000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ clocks = <&periph_clk>;
+ clock-names = "apb_pclk";
+ #dma-cells = <2>;
+ };
};
};
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* [PATCH v3 12/12] ARM64: dts: bcm63158: Add BCMBCA peripherals
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
` (10 preceding siblings ...)
2025-05-12 12:05 ` [PATCH v3 11/12] ARM64: dts: bcm6858: " Linus Walleij
@ 2025-05-12 12:05 ` Linus Walleij
2025-05-12 18:47 ` William Zhang
2025-05-13 8:58 ` Florian Fainelli
11 siblings, 2 replies; 36+ messages in thread
From: Linus Walleij @ 2025-05-12 12:05 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, William Zhang,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto, Linus Walleij
All the BCMBCA SoCs share a set of peripherals at 0xff800000,
albeit at slightly varying memory locations on the bus and
with varying IRQ assignments.
Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA
blocks for the BCM63158 based on the vendor files 63158_map_part.h
and 63158_intr.h from the "bcmopen-consumer" code drop.
The DTSI file has clearly been authored for the B0 revision of
the SoC: there is an earlier A0 version, but this has
the UARTs in the legacy PERF memory space, while the B0
has opened a new peripheral window at 0xff812000 for the
three UARTs. It also has a designated AHB peripheral area
at 0xff810000 where the DMA resides, the peripheral range
window fits these two peripheral groups.
This SoC has up to 256 possible GPIOs due to having 8
registers with 32 GPIOs in each available.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 129 ++++++++++++++++++++++
1 file changed, 129 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
index 48d618e75866452a64adfdc781ac0ea3c2eff3e8..a441388c0cd251d7dd5381f7b559633a89693232 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Broadcom Ltd.
+ * This DTSI is for the B0 and later revision of the SoC
*/
#include <dt-bindings/interrupt-controller/irq.h>
@@ -125,6 +126,101 @@ bus@ff800000 {
#size-cells = <1>;
ranges = <0x0 0x0 0xff800000 0x800000>;
+ /* GPIOs 0 .. 31 */
+ gpio0: gpio@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x500 0x04>, <0x520 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 32 .. 63 */
+ gpio1: gpio@504 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x504 0x04>, <0x524 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 64 .. 95 */
+ gpio2: gpio@508 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x508 0x04>, <0x528 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 96 .. 127 */
+ gpio3: gpio@50c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x50c 0x04>, <0x52c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 128 .. 159 */
+ gpio4: gpio@510 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x510 0x04>, <0x530 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 160 .. 191 */
+ gpio5: gpio@514 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x514 0x04>, <0x534 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 192 .. 223 */
+ gpio6: gpio@518 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x518 0x04>, <0x538 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ /* GPIOs 224 .. 255 */
+ gpio7: gpio@51c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x51c 0x04>, <0x53c 0x04>;
+ reg-names = "dirout", "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+
+ leds: led-controller@800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-leds";
+ reg = <0x800 0xdc>;
+ status = "disabled";
+ };
+
+ rng@b80 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0xb80 0x28>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
hsspi: spi@1000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -151,6 +247,21 @@ nandcs: nand@0 {
};
};
+ /* B0 AHB Peripherals */
+ pl081_dma: dma-controller@11000 {
+ compatible = "arm,pl081", "arm,primecell";
+ // The magic B105F00D info is missing
+ arm,primecell-periphid = <0x00041081>;
+ reg = <0x11000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ clocks = <&periph_clk>;
+ clock-names = "apb_pclk";
+ #dma-cells = <2>;
+ };
+
+ /* B0 ARM UART Peripheral block */
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
@@ -159,5 +270,23 @@ uart0: serial@12000 {
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ uart1: serial@13000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x13000 0x1000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ uart2: serial@14000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x14000 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
};
};
--
2.49.0
^ permalink raw reply related [flat|nested] 36+ messages in thread
* RE: [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number
2025-05-12 12:05 ` [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number Linus Walleij
@ 2025-05-12 18:33 ` William Zhang
2025-05-13 8:52 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:33 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 1973 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number
>
> According to the vendor file 6878_intr.h the UART0 has IRQ
> 92, not 32.
>
> Assuming this is a copy-and-paste error.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/boot/dts/broadcom/bcm6878.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> index
> 70cf23a65fdb5ac7ed9eabc986f4ebb4df263c43..43eb678e14d04be487af39c936
> 5186b6fb919cf3 100644
> --- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> @@ -137,7 +137,7 @@ nandcs: nand@0 {
> uart0: serial@12000 {
> compatible = "arm,pl011", "arm,primecell";
> reg = <0x12000 0x1000>;
> - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&uart_clk>, <&uart_clk>;
> clock-names = "uartclk", "apb_pclk";
> status = "disabled";
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG
2025-05-12 12:05 ` [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG Linus Walleij
@ 2025-05-12 18:34 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:34 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 1734 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG
>
> The r200 RNG has an interrupt so let's add it.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/boot/dts/broadcom/bcm6846.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm6846.dtsi
> b/arch/arm/boot/dts/broadcom/bcm6846.dtsi
> index
> e0e06af3fe891df3c3d8c2005cf1980d33a7762b..f5591a45d2e4ad64d8f95680ae
> a327771825252b 100644
> --- a/arch/arm/boot/dts/broadcom/bcm6846.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm6846.dtsi
> @@ -196,6 +196,7 @@ uart0: serial@640 {
> rng@b80 {
> compatible = "brcm,iproc-rng200";
> reg = <0xb80 0x28>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> leds: led-controller@800 {
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals Linus Walleij
@ 2025-05-12 18:35 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:35 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 5885 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the first and second watchdog, GPIO, RNG, LED, DMA and
> second PL011 UART blocks for the BCM6855 based on the vendor
> files 6855_map_part.h and 6855_intr.h from the
> "bcmopen-consumer" code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/boot/dts/broadcom/bcm6855.dtsi | 127
> ++++++++++++++++++++++++++++++++
> 1 file changed, 127 insertions(+)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm6855.dtsi
> b/arch/arm/boot/dts/broadcom/bcm6855.dtsi
> index
> 52915ec6f339335d87b4e50e1c03625fffb9a45d..a88c3f0fbcb037ee5c6b319334
> 15f90cb51ded2a 100644
> --- a/arch/arm/boot/dts/broadcom/bcm6855.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm6855.dtsi
> @@ -116,6 +116,103 @@ bus@ff800000 {
> #size-cells = <1>;
> ranges = <0 0xff800000 0x800000>;
>
> + watchdog@480 {
> + compatible = "brcm,bcm6345-wdt";
> + reg = <0x480 0x10>;
> + };
> +
> + watchdog@4c0 {
> + compatible = "brcm,bcm6345-wdt";
> + reg = <0x4c0 0x10>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 0 .. 31 */
> + gpio0: gpio@500 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x500 0x04>, <0x520 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 32 .. 63 */
> + gpio1: gpio@504 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x504 0x04>, <0x524 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 64 .. 95 */
> + gpio2: gpio@508 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x508 0x04>, <0x528 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 96 .. 127 */
> + gpio3: gpio@50c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x50c 0x04>, <0x52c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 128 .. 159 */
> + gpio4: gpio@510 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x510 0x04>, <0x530 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 160 .. 191 */
> + gpio5: gpio@514 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x514 0x04>, <0x534 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 192 .. 223 */
> + gpio6: gpio@518 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x518 0x04>, <0x538 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 224 .. 255 */
> + gpio7: gpio@51c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x51c 0x04>, <0x53c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + rng@b80 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0xb80 0x28>;
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> hsspi: spi@1000 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -143,6 +240,27 @@ nandcs: nand@0 {
> };
> };
>
> + leds: led-controller@3000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "brcm,bcm63138-leds";
> + reg = <0x3000 0xdc>;
> + status = "disabled";
> + };
> +
> + pl081_dma: dma-controller@11000 {
> + compatible = "arm,pl081", "arm,primecell";
> + // The magic B105F00D info is missing
> + arm,primecell-periphid = <0x00041081>;
> + reg = <0x11000 0x1000>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + memcpy-burst-size = <256>;
> + memcpy-bus-width = <32>;
> + clocks = <&periph_clk>;
> + clock-names = "apb_pclk";
> + #dma-cells = <2>;
> + };
> +
> uart0: serial@12000 {
> compatible = "arm,pl011", "arm,primecell";
> reg = <0x12000 0x1000>;
> @@ -151,5 +269,14 @@ uart0: serial@12000 {
> clock-names = "uartclk", "apb_pclk";
> status = "disabled";
> };
> +
> + uart1: serial@13000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x13000 0x1000>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_clk>, <&uart_clk>;
> + clock-names = "uartclk", "apb_pclk";
> + status = "disabled";
> + };
> };
> };
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 05/12] ARM: dts: bcm6878: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 05/12] ARM: dts: bcm6878: " Linus Walleij
@ 2025-05-12 18:37 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:37 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 5431 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 05/12] ARM: dts: bcm6878: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the first and second watchdog, GPIO, RNG, LED and
> DMA blocks for the BCM6878 based on the vendor files
> 6878_map_part.h and 6878_intr.h from the "bcmopen-consumer"
> code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/boot/dts/broadcom/bcm6878.dtsi | 118
> ++++++++++++++++++++++++++++++++
> 1 file changed, 118 insertions(+)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> index
> 43eb678e14d04be487af39c9365186b6fb919cf3..dd837bf693905736a7b8ef9cfe
> fea8368e6df6ed 100644
> --- a/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm6878.dtsi
> @@ -108,6 +108,111 @@ bus@ff800000 {
> #size-cells = <1>;
> ranges = <0 0xff800000 0x800000>;
>
> + watchdog@480 {
> + compatible = "brcm,bcm6345-wdt";
> + reg = <0x480 0x10>;
> + };
> +
> + watchdog@4c0 {
> + compatible = "brcm,bcm6345-wdt";
> + reg = <0x4c0 0x10>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 0 .. 31 */
> + gpio0: gpio@500 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x500 0x04>, <0x520 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 32 .. 63 */
> + gpio1: gpio@504 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x504 0x04>, <0x524 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 64 .. 95 */
> + gpio2: gpio@508 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x508 0x04>, <0x528 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 96 .. 127 */
> + gpio3: gpio@50c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x50c 0x04>, <0x52c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 128 .. 159 */
> + gpio4: gpio@510 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x510 0x04>, <0x530 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 160 .. 191 */
> + gpio5: gpio@514 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x514 0x04>, <0x534 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 192 .. 223 */
> + gpio6: gpio@518 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x518 0x04>, <0x538 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 224 .. 255 */
> + gpio7: gpio@51c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x51c 0x04>, <0x53c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + rng@b80 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0xb80 0x28>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + leds: led-controller@700 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "brcm,bcm63138-leds";
> + reg = <0x700 0xdc>;
> + status = "disabled";
> + };
> +
> hsspi: spi@1000 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -134,6 +239,19 @@ nandcs: nand@0 {
> };
> };
>
> + pl081_dma: dma-controller@11000 {
> + compatible = "arm,pl081", "arm,primecell";
> + // The magic B105F00D info is missing
> + arm,primecell-periphid = <0x00041081>;
> + reg = <0x11000 0x1000>;
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> + memcpy-burst-size = <256>;
> + memcpy-bus-width = <32>;
> + clocks = <&periph_clk>;
> + clock-names = "apb_pclk";
> + #dma-cells = <2>;
> + };
> +
> uart0: serial@12000 {
> compatible = "arm,pl011", "arm,primecell";
> reg = <0x12000 0x1000>;
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 06/12] ARM: dts: bcm63138: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 06/12] ARM: dts: bcm63138: " Linus Walleij
@ 2025-05-12 18:38 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:38 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 4884 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 06/12] ARM: dts: bcm63138: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Extend the peripheral interrupt window to 0x10000 as it need
> to fit the DMA block.
>
> Add the GPIO, RNG and LED and DMA blocks for the
> BCM63138 based on the vendor files 63138_map_part.h and
> 63138_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 160 possible GPIOs due to having 5
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/boot/dts/broadcom/bcm63138.dtsi | 79
> +++++++++++++++++++++++++++++++-
> 1 file changed, 78 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> index
> e74ba6bf370da63d3c115e38b4f20c71baff2116..4ec568586b14c89daceddea8f1
> 7381f72f512a93 100644
> --- a/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm63138.dtsi
> @@ -184,13 +184,69 @@ ubus@fffe8000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> - ranges = <0 0xfffe8000 0x8100>;
> + ranges = <0 0xfffe8000 0x10000>;
>
> timer: timer@80 {
> compatible = "brcm,bcm6328-timer", "syscon";
> reg = <0x80 0x3c>;
> };
>
> + /* GPIOs 0 .. 31 */
> + gpio0: gpio@100 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x100 0x04>, <0x114 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 32 .. 63 */
> + gpio1: gpio@104 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x104 0x04>, <0x118 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 64 .. 95 */
> + gpio2: gpio@108 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x108 0x04>, <0x11c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 96 .. 127 */
> + gpio3: gpio@10c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x10c 0x04>, <0x120 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 128 .. 159 */
> + gpio4: gpio@110 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x110 0x04>, <0x124 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + rng@300 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0x300 0x28>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> serial0: serial@600 {
> compatible = "brcm,bcm6345-uart";
> reg = <0x600 0x1b>;
> @@ -209,6 +265,14 @@ serial1: serial@620 {
> status = "disabled";
> };
>
> + leds: led-controller@700 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "brcm,bcm63138-leds";
> + reg = <0x700 0xdc>;
> + status = "disabled";
> + };
> +
> hsspi: spi@1000 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -248,6 +312,19 @@ bootlut: bootlut@8000 {
> reg = <0x8000 0x50>;
> };
>
> + pl081_dma: dma-controller@d000 {
> + compatible = "arm,pl081", "arm,primecell";
> + // The magic B105F00D info is missing
> + arm,primecell-periphid = <0x00041081>;
> + reg = <0xd000 0x1000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> + memcpy-burst-size = <256>;
> + memcpy-bus-width = <32>;
> + clocks = <&periph_clk>;
> + clock-names = "apb_pclk";
> + #dma-cells = <2>;
> + };
> +
> reboot {
> compatible = "syscon-reboot";
> regmap = <&timer>;
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 07/12] ARM: dts: bcm63148: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 07/12] ARM: dts: bcm63148: " Linus Walleij
@ 2025-05-12 18:38 ` William Zhang
2025-05-13 8:56 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:38 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 3956 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 07/12] ARM: dts: bcm63148: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the GPIO, RNG and LED and DMA blocks for the
> BCM63148 based on the vendor files 63148_map_part.h and
> 63148_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 160 possible GPIOs due to having 5
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/boot/dts/broadcom/bcm63148.dtsi | 64
> ++++++++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> index
> 53703827ee3fe58ead1dbe70536d7293ad842d0c..e071cddb28fc2888b8f408b4b
> c275290dd135642 100644
> --- a/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm63148.dtsi
> @@ -99,6 +99,62 @@ bus@ff800000 {
> #size-cells = <1>;
> ranges = <0 0xfffe8000 0x8000>;
>
> + /* GPIOs 0 .. 31 */
> + gpio0: gpio@100 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x100 0x04>, <0x114 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 32 .. 63 */
> + gpio1: gpio@104 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x104 0x04>, <0x118 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 64 .. 95 */
> + gpio2: gpio@108 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x108 0x04>, <0x11c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 96 .. 127 */
> + gpio3: gpio@10c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x10c 0x04>, <0x120 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 128 .. 159 */
> + gpio4: gpio@110 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x110 0x04>, <0x124 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + rng@300 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0x300 0x28>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> uart0: serial@600 {
> compatible = "brcm,bcm6345-uart";
> reg = <0x600 0x20>;
> @@ -108,6 +164,14 @@ uart0: serial@600 {
> status = "disabled";
> };
>
> + leds: led-controller@700 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "brcm,bcm63138-leds";
> + reg = <0x700 0xdc>;
> + status = "disabled";
> + };
> +
> hsspi: spi@1000 {
> #address-cells = <1>;
> #size-cells = <0>;
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 08/12] ARM: dts: bcm63178: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 08/12] ARM: dts: bcm63178: " Linus Walleij
@ 2025-05-12 18:39 ` William Zhang
2025-05-13 8:57 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:39 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 5290 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 08/12] ARM: dts: bcm63178: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the watchdog, GPIO, RNG, LED and DMA blocks for the
> BCM63178 based on the vendor files 63178_map_part.h and
> 63178_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm/boot/dts/broadcom/bcm63178.dtsi | 112
> +++++++++++++++++++++++++++++++
> 1 file changed, 112 insertions(+)
>
> diff --git a/arch/arm/boot/dts/broadcom/bcm63178.dtsi
> b/arch/arm/boot/dts/broadcom/bcm63178.dtsi
> index
> 6d8d33498983acfc0c65ee155f64ddedc4a6b376..430750b3030f2534d6bf0468d8
> 95ca565007a53f 100644
> --- a/arch/arm/boot/dts/broadcom/bcm63178.dtsi
> +++ b/arch/arm/boot/dts/broadcom/bcm63178.dtsi
> @@ -117,6 +117,97 @@ bus@ff800000 {
> #size-cells = <1>;
> ranges = <0 0xff800000 0x800000>;
>
> + watchdog@480 {
> + compatible = "brcm,bcm6345-wdt";
> + reg = <0x480 0x10>;
> + };
> +
> + /* GPIOs 0 .. 31 */
> + gpio0: gpio@500 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x500 0x04>, <0x520 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 32 .. 63 */
> + gpio1: gpio@504 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x504 0x04>, <0x524 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 64 .. 95 */
> + gpio2: gpio@508 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x508 0x04>, <0x528 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 96 .. 127 */
> + gpio3: gpio@50c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x50c 0x04>, <0x52c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 128 .. 159 */
> + gpio4: gpio@510 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x510 0x04>, <0x530 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 160 .. 191 */
> + gpio5: gpio@514 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x514 0x04>, <0x534 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 192 .. 223 */
> + gpio6: gpio@518 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x518 0x04>, <0x538 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 224 .. 255 */
> + gpio7: gpio@51c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x51c 0x04>, <0x53c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + rng@b80 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0xb80 0x28>;
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> hsspi: spi@1000 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -143,6 +234,27 @@ nandcs: nand@0 {
> };
> };
>
> + leds: led-controller@3000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "brcm,bcm63138-leds";
> + reg = <0x3000 0xdc>;
> + status = "disabled";
> + };
> +
> + pl081_dma: dma-controller@11000 {
> + compatible = "arm,pl081", "arm,primecell";
> + // The magic B105F00D info is missing
> + arm,primecell-periphid = <0x00041081>;
> + reg = <0x11000 0x1000>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + memcpy-burst-size = <256>;
> + memcpy-bus-width = <32>;
> + clocks = <&periph_clk>;
> + clock-names = "apb_pclk";
> + #dma-cells = <2>;
> + };
> +
> uart0: serial@12000 {
> compatible = "arm,pl011", "arm,primecell";
> reg = <0x12000 0x1000>;
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 09/12] ARM64: dts: bcm4908: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 09/12] ARM64: dts: bcm4908: " Linus Walleij
@ 2025-05-12 18:42 ` William Zhang
2025-05-13 8:57 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:42 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 6147 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 09/12] ARM64: dts: bcm4908: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments. ARM64 SoCs have additional
> peripherals at 0xff858000, we extend the peripheral bus
> range to 0x400000 to cover this area.
>
> Add the watchdog, remaining GPIO blocks, RNG, and DMA blocks
> for the BCM4908 based on the vendor files 4908_map_part.h
> and 4908_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 320 possible GPIOs due to having 10
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 116
> ++++++++++++++++++++++-
> 1 file changed, 113 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
> b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
> index
> 613ba7ee43d6489ea0f1490d2fccaf90961b2694..3b7595fd4e81d150278816bbe
> 27e08286cde2ff8 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
> @@ -323,11 +323,12 @@ pmb: power-controller@2800c0 {
> };
> };
>
> + /* PERF Peripherals */
> bus@ff800000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> - ranges = <0x00 0x00 0xff800000 0x3000>;
> + ranges = <0x00 0x00 0xff800000 0x400000>;
>
> twd: timer-mfd@400 {
> compatible = "brcm,bcm4908-twd", "simple-mfd",
> "syscon";
> @@ -348,13 +349,103 @@ watchdog@28 {
> };
> };
>
> - gpio0: gpio-controller@500 {
> + /* GPIOs 0 .. 31 */
> + gpio0: gpio@500 {
> compatible = "brcm,bcm6345-gpio";
> + reg = <0x500 0x04>, <0x528 0x04>;
> reg-names = "dirout", "dat";
> - reg = <0x500 0x28>, <0x528 0x28>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + /* GPIOs 32 .. 63 */
> + gpio1: gpio@504 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x504 0x04>, <0x52c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 64 .. 95 */
> + gpio2: gpio@508 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x508 0x04>, <0x530 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
>
> + /* GPIOs 96 .. 127 */
> + gpio3: gpio@50c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x50c 0x04>, <0x534 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 128 .. 159 */
> + gpio4: gpio@510 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x510 0x04>, <0x538 0x04>;
> + reg-names = "dirout", "dat";
> gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 160 .. 191 */
> + gpio5: gpio@514 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x514 0x04>, <0x53c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 192 .. 223 */
> + gpio6: gpio@518 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x518 0x04>, <0x540 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 224 .. 255 */
> + gpio7: gpio@51c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x51c 0x04>, <0x544 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 256 .. 287 */
> + gpio8: gpio@520 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x520 0x04>, <0x548 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 288 .. 319 */
> + gpio9: gpio@524 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x524 0x04>, <0x54c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> };
>
> pinctrl@560 {
> @@ -584,6 +675,12 @@ leds: leds@800 {
> #size-cells = <0>;
> };
>
> + rng@b80 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0xb80 0x28>;
> + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> hsspi: spi@1000 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -636,6 +733,19 @@ reset-controller@2644 {
> #reset-cells = <1>;
> };
> };
> +
> + pl081_dma: dma-controller@59000 {
> + compatible = "arm,pl081", "arm,primecell";
> + // The magic B105F00D info is missing
> + arm,primecell-periphid = <0x00041081>;
> + reg = <0x59000 0x1000>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + memcpy-burst-size = <256>;
> + memcpy-bus-width = <32>;
> + clocks = <&periph_clk>;
> + clock-names = "apb_pclk";
> + #dma-cells = <2>;
> + };
> };
>
> reboot {
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 10/12] ARM64: dts: bcm6856: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 10/12] ARM64: dts: bcm6856: " Linus Walleij
@ 2025-05-12 18:43 ` William Zhang
2025-05-13 8:58 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:43 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 6155 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 10/12] ARM64: dts: bcm6856: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments. ARM64 SoCs have additional
> peripherals at 0xff858000. Extend the BCM6856 the PERF window
> to 0x400000 and add the DMA block at offset 0x59000.
>
> Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA
> blocks for the BCM6856 based on the vendor files 6856_map_part.h
> and 6856_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 130
> ++++++++++++++++++++++-
> 1 file changed, 129 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
> b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
> index
> 00c62c1e5df00c722884a7adfcb7be08a43c0dc3..dcbd0fdd33d25fa340c417e828
> 4826801ebc00bb 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
> @@ -93,11 +93,103 @@ gic: interrupt-controller@1000 {
> };
> };
>
> + /* PERF Peripherals */
> bus@ff800000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> - ranges = <0x0 0x0 0xff800000 0x800000>;
> + ranges = <0x0 0x0 0xff800000 0x400000>;
> +
> + watchdog@480 {
> + compatible = "brcm,bcm6345-wdt";
> + reg = <0x480 0x10>;
> + };
> +
> + watchdog@4c0 {
> + compatible = "brcm,bcm6345-wdt";
> + reg = <0x4c0 0x10>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 0 .. 31 */
> + gpio0: gpio@500 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x500 0x04>, <0x520 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 32 .. 63 */
> + gpio1: gpio@504 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x504 0x04>, <0x524 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 64 .. 95 */
> + gpio2: gpio@508 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x508 0x04>, <0x528 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 96 .. 127 */
> + gpio3: gpio@50c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x50c 0x04>, <0x52c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 128 .. 159 */
> + gpio4: gpio@510 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x510 0x04>, <0x530 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 160 .. 191 */
> + gpio5: gpio@514 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x514 0x04>, <0x534 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 192 .. 223 */
> + gpio6: gpio@518 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x518 0x04>, <0x538 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 224 .. 255 */
> + gpio7: gpio@51c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x51c 0x04>, <0x53c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
>
> uart0: serial@640 {
> compatible = "brcm,bcm6345-uart";
> @@ -108,6 +200,29 @@ uart0: serial@640 {
> status = "disabled";
> };
>
> + uart1: serial@660 {
> + compatible = "brcm,bcm6345-uart";
> + reg = <0x660 0x18>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&periph_clk>;
> + clock-names = "refclk";
> + status = "disabled";
> + };
> +
> + leds: led-controller@800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "brcm,bcm63138-leds";
> + reg = <0x800 0xdc>;
> + status = "disabled";
> + };
> +
> + rng@b80 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0xb80 0x28>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> hsspi: spi@1000 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -133,5 +248,18 @@ nandcs: nand@0 {
> reg = <0>;
> };
> };
> +
> + pl081_dma: dma-controller@59000 {
> + compatible = "arm,pl081", "arm,primecell";
> + // The magic B105F00D info is missing
> + arm,primecell-periphid = <0x00041081>;
> + reg = <0x59000 0x1000>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + memcpy-burst-size = <256>;
> + memcpy-bus-width = <32>;
> + clocks = <&periph_clk>;
> + clock-names = "apb_pclk";
> + #dma-cells = <2>;
> + };
> };
> };
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 11/12] ARM64: dts: bcm6858: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 11/12] ARM64: dts: bcm6858: " Linus Walleij
@ 2025-05-12 18:44 ` William Zhang
2025-05-13 8:58 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:44 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 6109 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 11/12] ARM64: dts: bcm6858: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments. ARM64 SoCs have additional
> peripherals at 0xff858000. Extend the peripheral window range
> to 0x400000 and add the DMA controller at offset 0x59000.
>
> Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA
> blocks for the BCM6858 based on the vendor files 6858_map_part.h
> and 6858_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 119
> ++++++++++++++++++++++-
> 1 file changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> index
> caeaf428dc15db3089bf4dc62c4a272782c22c3f..c105a734a64897e714ed107e0d
> dccc5eebd415da 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
> @@ -111,11 +111,12 @@ gic: interrupt-controller@1000 {
> };
> };
>
> + /* PERF Peripherals */
> bus@ff800000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> - ranges = <0x0 0x0 0xff800000 0x62000>;
> + ranges = <0x0 0x0 0xff800000 0x400000>;
>
> twd: timer-mfd@400 {
> compatible = "brcm,bcm4908-twd", "simple-mfd",
> "syscon";
> @@ -136,6 +137,86 @@ watchdog@28 {
> };
> };
>
> + /* GPIOs 0 .. 31 */
> + gpio0: gpio@500 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x500 0x04>, <0x520 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 32 .. 63 */
> + gpio1: gpio@504 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x504 0x04>, <0x524 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 64 .. 95 */
> + gpio2: gpio@508 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x508 0x04>, <0x528 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 96 .. 127 */
> + gpio3: gpio@50c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x50c 0x04>, <0x52c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 128 .. 159 */
> + gpio4: gpio@510 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x510 0x04>, <0x530 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 160 .. 191 */
> + gpio5: gpio@514 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x514 0x04>, <0x534 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 192 .. 223 */
> + gpio6: gpio@518 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x518 0x04>, <0x538 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 224 .. 255 */
> + gpio7: gpio@51c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x51c 0x04>, <0x53c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> uart0: serial@640 {
> compatible = "brcm,bcm6345-uart";
> reg = <0x640 0x18>;
> @@ -145,6 +226,29 @@ uart0: serial@640 {
> status = "disabled";
> };
>
> + uart1: serial@660 {
> + compatible = "brcm,bcm6345-uart";
> + reg = <0x660 0x18>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&periph_clk>;
> + clock-names = "refclk";
> + status = "disabled";
> + };
> +
> + leds: led-controller@800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "brcm,bcm63138-leds";
> + reg = <0x800 0xdc>;
> + status = "disabled";
> + };
> +
> + rng@b80 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0xb80 0x28>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> hsspi: spi@1000 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -170,5 +274,18 @@ nandcs: nand@0 {
> reg = <0>;
> };
> };
> +
> + pl081_dma: dma-controller@59000 {
> + compatible = "arm,pl081", "arm,primecell";
> + // The magic B105F00D info is missing
> + arm,primecell-periphid = <0x00041081>;
> + reg = <0x59000 0x1000>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + memcpy-burst-size = <256>;
> + memcpy-bus-width = <32>;
> + clocks = <&periph_clk>;
> + clock-names = "apb_pclk";
> + #dma-cells = <2>;
> + };
> };
> };
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* RE: [PATCH v3 12/12] ARM64: dts: bcm63158: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 12/12] ARM64: dts: bcm63158: " Linus Walleij
@ 2025-05-12 18:47 ` William Zhang
2025-05-13 8:58 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: William Zhang @ 2025-05-12 18:47 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Anand Gore, Kursad Oney, Florian Fainelli,
Rafał Miłecki, Broadcom internal kernel review list,
Olivia Mackall, Ray Jui, Scott Branden, Florian Fainelli
Cc: devicetree, linux-arm-kernel, linux-crypto
[-- Attachment #1: Type: text/plain, Size: 6701 bytes --]
> -----Original Message-----
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Monday, May 12, 2025 5:06 AM
> To: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>;
> Conor Dooley <conor+dt@kernel.org>; William Zhang
> <william.zhang@broadcom.com>; Anand Gore <anand.gore@broadcom.com>;
> Kursad Oney <kursad.oney@broadcom.com>; Florian Fainelli
> <florian.fainelli@broadcom.com>; Rafał Miłecki <rafal@milecki.pl>;
> Broadcom
> internal kernel review list <bcm-kernel-feedback-list@broadcom.com>;
> Olivia
> Mackall <olivia@selenic.com>; Ray Jui <rjui@broadcom.com>; Scott Branden
> <sbranden@broadcom.com>; Florian Fainelli <f.fainelli@gmail.com>
> Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-
> crypto@vger.kernel.org; Linus Walleij <linus.walleij@linaro.org>
> Subject: [PATCH v3 12/12] ARM64: dts: bcm63158: Add BCMBCA peripherals
>
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA
> blocks for the BCM63158 based on the vendor files 63158_map_part.h
> and 63158_intr.h from the "bcmopen-consumer" code drop.
>
> The DTSI file has clearly been authored for the B0 revision of
> the SoC: there is an earlier A0 version, but this has
> the UARTs in the legacy PERF memory space, while the B0
> has opened a new peripheral window at 0xff812000 for the
> three UARTs. It also has a designated AHB peripheral area
> at 0xff810000 where the DMA resides, the peripheral range
> window fits these two peripheral groups.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 129
> ++++++++++++++++++++++
> 1 file changed, 129 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
> b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
> index
> 48d618e75866452a64adfdc781ac0ea3c2eff3e8..a441388c0cd251d7dd5381f7b5
> 59633a89693232 100644
> --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
> +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> * Copyright 2022 Broadcom Ltd.
> + * This DTSI is for the B0 and later revision of the SoC
> */
>
> #include <dt-bindings/interrupt-controller/irq.h>
> @@ -125,6 +126,101 @@ bus@ff800000 {
> #size-cells = <1>;
> ranges = <0x0 0x0 0xff800000 0x800000>;
>
> + /* GPIOs 0 .. 31 */
> + gpio0: gpio@500 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x500 0x04>, <0x520 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 32 .. 63 */
> + gpio1: gpio@504 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x504 0x04>, <0x524 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 64 .. 95 */
> + gpio2: gpio@508 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x508 0x04>, <0x528 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 96 .. 127 */
> + gpio3: gpio@50c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x50c 0x04>, <0x52c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 128 .. 159 */
> + gpio4: gpio@510 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x510 0x04>, <0x530 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 160 .. 191 */
> + gpio5: gpio@514 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x514 0x04>, <0x534 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 192 .. 223 */
> + gpio6: gpio@518 {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x518 0x04>, <0x538 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> + /* GPIOs 224 .. 255 */
> + gpio7: gpio@51c {
> + compatible = "brcm,bcm6345-gpio";
> + reg = <0x51c 0x04>, <0x53c 0x04>;
> + reg-names = "dirout", "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + status = "disabled";
> + };
> +
> +
> + leds: led-controller@800 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "brcm,bcm63138-leds";
> + reg = <0x800 0xdc>;
> + status = "disabled";
> + };
> +
> + rng@b80 {
> + compatible = "brcm,iproc-rng200";
> + reg = <0xb80 0x28>;
> + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> hsspi: spi@1000 {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -151,6 +247,21 @@ nandcs: nand@0 {
> };
> };
>
> + /* B0 AHB Peripherals */
> + pl081_dma: dma-controller@11000 {
> + compatible = "arm,pl081", "arm,primecell";
> + // The magic B105F00D info is missing
> + arm,primecell-periphid = <0x00041081>;
> + reg = <0x11000 0x1000>;
> + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> + memcpy-burst-size = <256>;
> + memcpy-bus-width = <32>;
> + clocks = <&periph_clk>;
> + clock-names = "apb_pclk";
> + #dma-cells = <2>;
> + };
> +
> + /* B0 ARM UART Peripheral block */
> uart0: serial@12000 {
> compatible = "arm,pl011", "arm,primecell";
> reg = <0x12000 0x1000>;
> @@ -159,5 +270,23 @@ uart0: serial@12000 {
> clock-names = "uartclk", "apb_pclk";
> status = "disabled";
> };
> +
> + uart1: serial@13000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x13000 0x1000>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_clk>, <&uart_clk>;
> + clock-names = "uartclk", "apb_pclk";
> + status = "disabled";
> + };
> +
> + uart2: serial@14000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x14000 0x1000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_clk>, <&uart_clk>;
> + clock-names = "uartclk", "apb_pclk";
> + status = "disabled";
> + };
> };
> };
>
> --
> 2.49.0
Reviewed-by: William Zhang <william.zhang@broadcom.com>
[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4199 bytes --]
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number
2025-05-12 12:05 ` [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number Linus Walleij
2025-05-12 18:33 ` William Zhang
@ 2025-05-13 8:52 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:52 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:47 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> According to the vendor file 6878_intr.h the UART0 has IRQ
> 92, not 32.
>
> Assuming this is a copy-and-paste error.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 02/12] dt-bindings: rng: r200: Add interrupt property
2025-05-12 12:05 ` [PATCH v3 02/12] dt-bindings: rng: r200: Add interrupt property Linus Walleij
@ 2025-05-13 8:52 ` Florian Fainelli
0 siblings, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:52 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto,
Krzysztof Kozlowski
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:48 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> This IP block has an interrupt. Add it and add it to the
> example as well.
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG
2025-05-12 12:05 ` [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG Linus Walleij
2025-05-12 18:34 ` William Zhang
@ 2025-05-13 8:55 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:55 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:49 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> The r200 RNG has an interrupt so let's add it.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals Linus Walleij
2025-05-12 18:35 ` William Zhang
@ 2025-05-13 8:55 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:55 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:50 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the first and second watchdog, GPIO, RNG, LED, DMA and
> second PL011 UART blocks for the BCM6855 based on the vendor
> files 6855_map_part.h and 6855_intr.h from the
> "bcmopen-consumer" code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 05/12] ARM: dts: bcm6878: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 05/12] ARM: dts: bcm6878: " Linus Walleij
2025-05-12 18:37 ` William Zhang
@ 2025-05-13 8:55 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:55 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:51 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the first and second watchdog, GPIO, RNG, LED and
> DMA blocks for the BCM6878 based on the vendor files
> 6878_map_part.h and 6878_intr.h from the "bcmopen-consumer"
> code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 06/12] ARM: dts: bcm63138: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 06/12] ARM: dts: bcm63138: " Linus Walleij
2025-05-12 18:38 ` William Zhang
@ 2025-05-13 8:55 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:55 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:52 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Extend the peripheral interrupt window to 0x10000 as it need
> to fit the DMA block.
>
> Add the GPIO, RNG and LED and DMA blocks for the
> BCM63138 based on the vendor files 63138_map_part.h and
> 63138_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 160 possible GPIOs due to having 5
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 07/12] ARM: dts: bcm63148: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 07/12] ARM: dts: bcm63148: " Linus Walleij
2025-05-12 18:38 ` William Zhang
@ 2025-05-13 8:56 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:56 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:53 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the GPIO, RNG and LED and DMA blocks for the
> BCM63148 based on the vendor files 63148_map_part.h and
> 63148_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 160 possible GPIOs due to having 5
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 08/12] ARM: dts: bcm63178: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 08/12] ARM: dts: bcm63178: " Linus Walleij
2025-05-12 18:39 ` William Zhang
@ 2025-05-13 8:57 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:57 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:54 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the watchdog, GPIO, RNG, LED and DMA blocks for the
> BCM63178 based on the vendor files 63178_map_part.h and
> 63178_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 09/12] ARM64: dts: bcm4908: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 09/12] ARM64: dts: bcm4908: " Linus Walleij
2025-05-12 18:42 ` William Zhang
@ 2025-05-13 8:57 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:57 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:55 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments. ARM64 SoCs have additional
> peripherals at 0xff858000, we extend the peripheral bus
> range to 0x400000 to cover this area.
>
> Add the watchdog, remaining GPIO blocks, RNG, and DMA blocks
> for the BCM4908 based on the vendor files 4908_map_part.h
> and 4908_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 320 possible GPIOs due to having 10
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 10/12] ARM64: dts: bcm6856: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 10/12] ARM64: dts: bcm6856: " Linus Walleij
2025-05-12 18:43 ` William Zhang
@ 2025-05-13 8:58 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:58 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:56 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments. ARM64 SoCs have additional
> peripherals at 0xff858000. Extend the BCM6856 the PERF window
> to 0x400000 and add the DMA block at offset 0x59000.
>
> Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA
> blocks for the BCM6856 based on the vendor files 6856_map_part.h
> and 6856_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 11/12] ARM64: dts: bcm6858: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 11/12] ARM64: dts: bcm6858: " Linus Walleij
2025-05-12 18:44 ` William Zhang
@ 2025-05-13 8:58 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:58 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:57 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments. ARM64 SoCs have additional
> peripherals at 0xff858000. Extend the peripheral window range
> to 0x400000 and add the DMA controller at offset 0x59000.
>
> Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA
> blocks for the BCM6858 based on the vendor files 6858_map_part.h
> and 6858_intr.h from the "bcmopen-consumer" code drop.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
* Re: [PATCH v3 12/12] ARM64: dts: bcm63158: Add BCMBCA peripherals
2025-05-12 12:05 ` [PATCH v3 12/12] ARM64: dts: bcm63158: " Linus Walleij
2025-05-12 18:47 ` William Zhang
@ 2025-05-13 8:58 ` Florian Fainelli
1 sibling, 0 replies; 36+ messages in thread
From: Florian Fainelli @ 2025-05-13 8:58 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, William Zhang, Anand Gore,
Kursad Oney, Florian Fainelli, Rafał Miłecki,
Olivia Mackall, Ray Jui, Scott Branden
Cc: Florian Fainelli, devicetree, linux-arm-kernel, linux-crypto
From: Florian Fainelli <f.fainelli@gmail.com>
On Mon, 12 May 2025 14:05:58 +0200, Linus Walleij <linus.walleij@linaro.org> wrote:
> All the BCMBCA SoCs share a set of peripherals at 0xff800000,
> albeit at slightly varying memory locations on the bus and
> with varying IRQ assignments.
>
> Add the watchdog, GPIO blocks, RNG, LED, second UART and DMA
> blocks for the BCM63158 based on the vendor files 63158_map_part.h
> and 63158_intr.h from the "bcmopen-consumer" code drop.
>
> The DTSI file has clearly been authored for the B0 revision of
> the SoC: there is an earlier A0 version, but this has
> the UARTs in the legacy PERF memory space, while the B0
> has opened a new peripheral window at 0xff812000 for the
> three UARTs. It also has a designated AHB peripheral area
> at 0xff810000 where the DMA resides, the peripheral range
> window fits these two peripheral groups.
>
> This SoC has up to 256 possible GPIOs due to having 8
> registers with 32 GPIOs in each available.
>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 36+ messages in thread
end of thread, other threads:[~2025-05-13 9:17 UTC | newest]
Thread overview: 36+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-12 12:05 [PATCH v3 00/12] ARM: bcm: Add some BCMBCA peripherals Linus Walleij
2025-05-12 12:05 ` [PATCH v3 01/12] ARM: dts: bcm6878: Correct UART0 IRQ number Linus Walleij
2025-05-12 18:33 ` William Zhang
2025-05-13 8:52 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 02/12] dt-bindings: rng: r200: Add interrupt property Linus Walleij
2025-05-13 8:52 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 03/12] ARM: dts: bcm6846: Add interrupt to RNG Linus Walleij
2025-05-12 18:34 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 04/12] ARM: dts: bcm6855: Add BCMBCA peripherals Linus Walleij
2025-05-12 18:35 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 05/12] ARM: dts: bcm6878: " Linus Walleij
2025-05-12 18:37 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 06/12] ARM: dts: bcm63138: " Linus Walleij
2025-05-12 18:38 ` William Zhang
2025-05-13 8:55 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 07/12] ARM: dts: bcm63148: " Linus Walleij
2025-05-12 18:38 ` William Zhang
2025-05-13 8:56 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 08/12] ARM: dts: bcm63178: " Linus Walleij
2025-05-12 18:39 ` William Zhang
2025-05-13 8:57 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 09/12] ARM64: dts: bcm4908: " Linus Walleij
2025-05-12 18:42 ` William Zhang
2025-05-13 8:57 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 10/12] ARM64: dts: bcm6856: " Linus Walleij
2025-05-12 18:43 ` William Zhang
2025-05-13 8:58 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 11/12] ARM64: dts: bcm6858: " Linus Walleij
2025-05-12 18:44 ` William Zhang
2025-05-13 8:58 ` Florian Fainelli
2025-05-12 12:05 ` [PATCH v3 12/12] ARM64: dts: bcm63158: " Linus Walleij
2025-05-12 18:47 ` William Zhang
2025-05-13 8:58 ` Florian Fainelli
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).