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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fdac667sm124168766b.58.2025.11.13.01.42.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Nov 2025 01:42:57 -0800 (PST) Message-ID: Date: Thu, 13 Nov 2025 10:42:53 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 12/21] drm/msm/a6xx: Share dependency vote table with GMU To: Akhil P Oommen , Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20251110-kaana-gpu-support-v2-0-bef18acd5e94@oss.qualcomm.com> <20251110-kaana-gpu-support-v2-12-bef18acd5e94@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251110-kaana-gpu-support-v2-12-bef18acd5e94@oss.qualcomm.com> Content-Type: text/plain; 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> } > > +static int a6xx_gmu_rpmh_dep_votes_init(struct device *dev, u32 *votes, > + unsigned long *freqs, int freqs_count) Checkpatch should be grumpy about indentation here [...] > + /* Construct a vote for rest of the corners */ > + for (int i = 1; i < freqs_count; i++) { > + u8 j, index = 0; > + unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]); nit: reverse-Christmas-tree would be nice here > + > + /* Get the primary index that matches the arc level */ > + for (j = 0; j < count; j++) { > + if (mx[j] >= level) { > + index = j; > + break; > + } > + } > + > + if (j == count) { > + DRM_DEV_ERROR(dev, > + "Mx Level %u not found in the RPMh list\n", > + level); > + DRM_DEV_ERROR(dev, "Available levels:\n"); > + for (j = 0; j < count; j++) > + DRM_DEV_ERROR(dev, " %u\n", mx[j]); > + > + return -EINVAL; > + } > + > + /* Construct the vote */ > + votes[i] = (0x3fff << 14) | (index << 8) | (0xff); FIELD_PREP() + GENMASK, please [...] > +static int a8xx_hfi_send_perf_table(struct a6xx_gmu *gmu) > +{ > + unsigned int num_gx_votes = 3, num_cx_votes = 2; > + struct a6xx_hfi_table_entry *entry; > + struct a6xx_hfi_table *tbl; > + int ret, i; > + u32 size; > + > + size = sizeof(*tbl) + (2 * sizeof(tbl->entry[0])) + > + (gmu->nr_gpu_freqs * num_gx_votes * sizeof(gmu->gx_arc_votes[0])) + > + (gmu->nr_gmu_freqs * num_cx_votes * sizeof(gmu->cx_arc_votes[0])); > + tbl = devm_kzalloc(gmu->dev, size, GFP_KERNEL); devm_ only adds overhead here, there's not even an error-return path, go with regular kzalloc/kfree > + tbl->type = HFI_TABLE_GPU_PERF; > + > + /* First fill GX votes */ > + entry = &tbl->entry[0]; > + entry->count = gmu->nr_gpu_freqs; > + entry->stride = num_gx_votes; > + > + for (i = 0; i < gmu->nr_gpu_freqs; i++) { > + unsigned int base = i * entry->stride; > + > + entry->data[base+0] = gmu->gx_arc_votes[i]; > + entry->data[base+1] = gmu->dep_arc_votes[i]; > + entry->data[base+2] = gmu->gpu_freqs[i] / 1000; This is essentially struct perf_gx_level with the ACD field recycled > + } > + > + /* Then fill CX votes */ > + entry = (struct a6xx_hfi_table_entry *) > + &tbl->entry[0].data[gmu->nr_gpu_freqs * num_gx_votes]; > + > + entry->count = gmu->nr_gmu_freqs; > + entry->stride = num_cx_votes; > + > + for (i = 0; i < gmu->nr_gmu_freqs; i++) { > + unsigned int base = i * entry->stride; > + > + entry->data[base] = gmu->cx_arc_votes[i]; > + entry->data[base+1] = gmu->gmu_freqs[i] / 1000; And this is struct perf_level [...] > +#define HFI_H2F_MSG_TABLE 15 > + > +struct a6xx_hfi_table_entry { > + u32 count; > + u32 stride; > + u32 data[]; > +}; > + > +struct a6xx_hfi_table { > + u32 header; > + u32 version; > +#define HFI_TABLE_BW_VOTE 0 > +#define HFI_TABLE_GPU_PERF 1 Such defines usually go below the field definition, not above Konrad > + u32 type; > + struct a6xx_hfi_table_entry entry[]; > +}; > + > #define HFI_H2F_MSG_GX_BW_PERF_VOTE 30 > > struct a6xx_hfi_gx_bw_perf_vote_cmd { >