* [PATCH 1/7] arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
@ 2026-03-04 17:10 ` Geert Uytterhoeven
2026-03-06 10:12 ` Neil Armstrong
2026-03-04 17:10 ` [PATCH 2/7] arm64: dts: exynos: gs101: " Geert Uytterhoeven
` (9 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-03-04 17:10 UTC (permalink / raw)
To: Marc Zyngier, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel,
Geert Uytterhoeven
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
While at it, replace the magic number for IRQ_TYPE_LEVEL_HIGH by its
symbolic definition.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
index 8ef6319390331fcf..ab3acef2b147e62c 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
@@ -53,10 +53,10 @@ pwrc: power-controller {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@@ -84,7 +84,7 @@ gic: interrupt-controller@ff200000 {
interrupt-controller;
reg = <0x0 0xff200000 0 0x10000>,
<0x0 0xff240000 0 0x80000>;
- interrupts = <GIC_PPI 9 0xf04>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
apb: bus@fe000000 {
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 1/7] arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 ` [PATCH 1/7] arm64: dts: amlogic: s6: " Geert Uytterhoeven
@ 2026-03-06 10:12 ` Neil Armstrong
0 siblings, 0 replies; 18+ messages in thread
From: Neil Armstrong @ 2026-03-06 10:12 UTC (permalink / raw)
To: Geert Uytterhoeven, Marc Zyngier, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel
On 3/4/26 18:10, Geert Uytterhoeven wrote:
> Unlike older GIC variants, the GICv3 DT bindings do not support
> specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
> While at it, replace the magic number for IRQ_TYPE_LEVEL_HIGH by its
> symbolic definition.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
> index 8ef6319390331fcf..ab3acef2b147e62c 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-s6.dtsi
> @@ -53,10 +53,10 @@ pwrc: power-controller {
>
> timer {
> compatible = "arm,armv8-timer";
> - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> };
>
> psci {
> @@ -84,7 +84,7 @@ gic: interrupt-controller@ff200000 {
> interrupt-controller;
> reg = <0x0 0xff200000 0 0x10000>,
> <0x0 0xff240000 0 0x80000>;
> - interrupts = <GIC_PPI 9 0xf04>;
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> apb: bus@fe000000 {
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 2/7] arm64: dts: exynos: gs101: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
2026-03-04 17:10 ` [PATCH 1/7] arm64: dts: amlogic: s6: " Geert Uytterhoeven
@ 2026-03-04 17:10 ` Geert Uytterhoeven
2026-03-04 17:11 ` [PATCH 3/7] arm64: dts: fsl-ls1028a: " Geert Uytterhoeven
` (8 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-03-04 17:10 UTC (permalink / raw)
To: Marc Zyngier, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel,
Geert Uytterhoeven
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index d085f9fb0f62ac2f..2d372d667f79c9d1 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1853,10 +1853,10 @@ apm_sram: sram@2039000 {
timer {
compatible = "arm,armv8-timer";
interrupts =
- <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
+ <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
};
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 3/7] arm64: dts: fsl-ls1028a: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
2026-03-04 17:10 ` [PATCH 1/7] arm64: dts: amlogic: s6: " Geert Uytterhoeven
2026-03-04 17:10 ` [PATCH 2/7] arm64: dts: exynos: gs101: " Geert Uytterhoeven
@ 2026-03-04 17:11 ` Geert Uytterhoeven
2026-03-04 17:11 ` [PATCH 4/7] arm64: dts: freescale: imx: " Geert Uytterhoeven
` (7 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-03-04 17:11 UTC (permalink / raw)
To: Marc Zyngier, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel,
Geert Uytterhoeven
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index e7f9c9319319a69d..f4ba3d16ab86d660 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -114,14 +114,10 @@ optee: optee {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
@@ -138,8 +134,7 @@ gic: interrupt-controller@6000000 {
<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
#interrupt-cells = <3>;
interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
- IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
its: msi-controller@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 4/7] arm64: dts: freescale: imx: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
` (2 preceding siblings ...)
2026-03-04 17:11 ` [PATCH 3/7] arm64: dts: fsl-ls1028a: " Geert Uytterhoeven
@ 2026-03-04 17:11 ` Geert Uytterhoeven
2026-03-04 17:11 ` [PATCH 5/7] arm64: dts: intel: agilex5: " Geert Uytterhoeven
` (6 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-03-04 17:11 UTC (permalink / raw)
To: Marc Zyngier, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel,
Geert Uytterhoeven
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 11 +++++------
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 11 +++++------
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 11 +++++------
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 3 +--
arch/arm64/boot/dts/freescale/imx91_93_common.dtsi | 10 +++++-----
arch/arm64/boot/dts/freescale/imx94.dtsi | 10 +++++-----
arch/arm64/boot/dts/freescale/imx95.dtsi | 10 +++++-----
arch/arm64/boot/dts/freescale/imx952.dtsi | 10 +++++-----
8 files changed, 36 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 9f49c0b386d31051..3331b12b9294f339 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -220,16 +220,15 @@ psci {
pmu {
compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 3199bc0966b03905..79b169b07c4fc95d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -215,8 +215,7 @@ clk_ext4: clock-ext4 {
pmu {
compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@@ -258,10 +257,10 @@ map0 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9b2b3a9bf9e80ca8..90d7bb8f5619e50d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -310,8 +310,7 @@ dsp_reserved: dsp@92400000 {
pmu {
compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7
- (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@@ -397,10 +396,10 @@ map0 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
};
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 9b5d987665129e0c..1de3ad60c6aa7791 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -86,8 +86,7 @@ gic: interrupt-controller@2d400000 {
pmu {
compatible = "arm,cortex-a35-pmu";
interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 7
- (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A35_0>, <&A35_1>;
};
diff --git a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
index 7958cef353766a43..aa7aaf134a2fc41d 100644
--- a/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
@@ -69,7 +69,7 @@ clk_ext1: clock-ext1 {
pmu {
compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@@ -79,10 +79,10 @@ psci {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
arm,no-tick-in-suspend;
interrupt-parent = <&gic>;
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index d2f31c8caf6eb781..4793dee2537c40d0 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -120,7 +120,7 @@ mqs2: mqs2 {
pmu {
compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@@ -130,10 +130,10 @@ psci {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
interrupt-parent = <&gic>;
arm,no-tick-in-suspend;
diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 55e2da094c889fc7..cc563ffa8af5229c 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -393,7 +393,7 @@ scmi_misc: protocol@84 {
pmu {
compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
thermal_zones: thermal-zones {
@@ -470,10 +470,10 @@ psci {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
arm,no-tick-in-suspend;
interrupt-parent = <&gic>;
diff --git a/arch/arm64/boot/dts/freescale/imx952.dtsi b/arch/arm64/boot/dts/freescale/imx952.dtsi
index 91fe4916ac04d1d6..3d1dc9a8d18093bf 100644
--- a/arch/arm64/boot/dts/freescale/imx952.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx952.dtsi
@@ -285,7 +285,7 @@ its: msi-controller@48040000 {
pmu {
compatible = "arm,cortex-a55-pmu";
- interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
@@ -295,10 +295,10 @@ psci {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <24000000>;
arm,no-tick-in-suspend;
interrupt-parent = <&gic>;
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 5/7] arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
` (3 preceding siblings ...)
2026-03-04 17:11 ` [PATCH 4/7] arm64: dts: freescale: imx: " Geert Uytterhoeven
@ 2026-03-04 17:11 ` Geert Uytterhoeven
2026-03-11 2:12 ` Dinh Nguyen
2026-03-04 17:11 ` [PATCH 6/7] arm64: tegra: " Geert Uytterhoeven
` (5 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-03-04 17:11 UTC (permalink / raw)
To: Marc Zyngier, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel,
Geert Uytterhoeven
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 352c96d144a84102..02e62d954e94905d 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -152,10 +152,10 @@ qspi_clk: qspi-clk {
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
usbphy0: usbphy {
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 5/7] arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:11 ` [PATCH 5/7] arm64: dts: intel: agilex5: " Geert Uytterhoeven
@ 2026-03-11 2:12 ` Dinh Nguyen
0 siblings, 0 replies; 18+ messages in thread
From: Dinh Nguyen @ 2026-03-11 2:12 UTC (permalink / raw)
To: Geert Uytterhoeven, Marc Zyngier, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Peter Griffin,
André Draszik, Tudor Ambarus, Alim Akhtar, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel
On 3/4/26 11:11, Geert Uytterhoeven wrote:
> Unlike older GIC variants, the GICv3 DT bindings do not support
> specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 352c96d144a84102..02e62d954e94905d 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -152,10 +152,10 @@ qspi_clk: qspi-clk {
> timer {
> compatible = "arm,armv8-timer";
> interrupt-parent = <&intc>;
> - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> };
>
> usbphy0: usbphy {
Applied!
Thanks,
Dinh
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 6/7] arm64: tegra: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
` (4 preceding siblings ...)
2026-03-04 17:11 ` [PATCH 5/7] arm64: dts: intel: agilex5: " Geert Uytterhoeven
@ 2026-03-04 17:11 ` Geert Uytterhoeven
2026-03-04 17:11 ` [PATCH 7/7] arm64: dts: qcom: " Geert Uytterhoeven
` (4 subsequent siblings)
10 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-03-04 17:11 UTC (permalink / raw)
To: Marc Zyngier, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel,
Geert Uytterhoeven
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 850c473235e367ac..24ee589396cb18b4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -4083,7 +4083,7 @@ gic: interrupt-controller@f400000 {
reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
<0x0 0x0f440000 0x0 0x200000>; /* GICR */
interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#redistributor-regions = <1>;
#interrupt-cells = <3>;
@@ -5869,10 +5869,10 @@ tj-thermal {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gic>;
always-on;
};
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 7/7] arm64: dts: qcom: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
` (5 preceding siblings ...)
2026-03-04 17:11 ` [PATCH 6/7] arm64: tegra: " Geert Uytterhoeven
@ 2026-03-04 17:11 ` Geert Uytterhoeven
2026-03-05 10:02 ` Konrad Dybcio
2026-03-05 9:33 ` [PATCH 0/7] arm64: dts: " Konrad Dybcio
` (3 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-03-04 17:11 UTC (permalink / raw)
To: Marc Zyngier, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel,
Geert Uytterhoeven
Unlike older GIC variants, the GICv3 DT bindings do not support
specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/qcom/agatti.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/lemans.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/monaco.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 +++++-----
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sdm630.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sdx75.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm4450.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm6115.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm6125.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm6350.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm6375.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++--------
arch/arm64/boot/dts/qcom/sm8350.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/sm8550.dtsi | 8 ++++----
arch/arm64/boot/dts/qcom/talos.dtsi | 8 ++++----
17 files changed, 69 insertions(+), 73 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi
index 76b93b7bd50f9c61..6ee71c3895a9d402 100644
--- a/arch/arm64/boot/dts/qcom/agatti.dtsi
+++ b/arch/arm64/boot/dts/qcom/agatti.dtsi
@@ -2839,9 +2839,9 @@ camera_crit: camera-crit {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index 808827b83553dd70..09226bbc2aa6d6e3 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -8575,10 +8575,10 @@ trip-point1 {
arch_timer: timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
turing-llm-tpdm {
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 5d2df4305d1c1c45..372518ab7f1c08dc 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -7707,9 +7707,9 @@ cpuss1-critical {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index cdfe40da5d333297..952d4270d1181eb5 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -1638,10 +1638,10 @@ multi_chan_ddr: multi-chan-ddr@12b {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 706eb1309d3f0844..1f41295433561f94 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -6652,9 +6652,9 @@ trip-point0 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi
index f4b8e8f468f2479d..0b6448650471a798 100644
--- a/arch/arm64/boot/dts/qcom/sdm630.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi
@@ -2755,10 +2755,10 @@ trip-point2 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi
index eff4c9055d663da7..d1b61530b562f019 100644
--- a/arch/arm64/boot/dts/qcom/sdx75.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi
@@ -1580,9 +1580,9 @@ gem_noc: interconnect@19100000 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index d217d922811e8442..696e2e0841ad9ab0 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -678,9 +678,9 @@ cpufreq_hw: cpufreq@17d91000 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index e9336adbc3918437..a2a6cdad9a97b836 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -3460,9 +3460,9 @@ trip-point1 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 80c42dff5399b7c6..31cff36144c569a2 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -1592,10 +1592,10 @@ intc: interrupt-controller@f200000 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <19200000>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 9f9b9f9af0da9ddd..70f61c6b6ff6a313 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -3509,9 +3509,9 @@ video-crit {
timer {
compatible = "arm,armv8-timer";
clock-frequency = <19200000>;
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index 87d6600ccbd94e60..ccf572bb1549bf6b 100644
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -2469,9 +2469,9 @@ video_crit: video-crit {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index c7dffa440074073b..c511b516327487b6 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -6285,14 +6285,10 @@ sound: sound {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
thermal-zones {
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 5c8fe213f5e4ecbb..bc07c51049e7ace2 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -4523,9 +4523,9 @@ camera2_alert0: trip-point0 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 920a2d1c04d0c5a8..3e5b4b1c2406b83f 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -6327,10 +6327,10 @@ reset-mon-cfg {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
clock-frequency = <19200000>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index e3f93f4f412ded95..980ced8c961e465b 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -6758,9 +6758,9 @@ trip-point2 {
timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
};
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index 75716b4a58d6d331..b1c3abcc2fc896a9 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -4714,10 +4714,10 @@ cpufreq_hw: cpufreq@18323000 {
arch_timer: timer {
compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>,
- <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW) 0>;
+ interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW 0>;
};
thermal-zones {
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH 7/7] arm64: dts: qcom: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:11 ` [PATCH 7/7] arm64: dts: qcom: " Geert Uytterhoeven
@ 2026-03-05 10:02 ` Konrad Dybcio
0 siblings, 0 replies; 18+ messages in thread
From: Konrad Dybcio @ 2026-03-05 10:02 UTC (permalink / raw)
To: Geert Uytterhoeven, Marc Zyngier, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Peter Griffin,
André Draszik, Tudor Ambarus, Alim Akhtar, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel
On 3/4/26 6:11 PM, Geert Uytterhoeven wrote:
> Unlike older GIC variants, the GICv3 DT bindings do not support
> specifying a CPU mask in PPI interrupt specifiers. Drop the masks.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
` (6 preceding siblings ...)
2026-03-04 17:11 ` [PATCH 7/7] arm64: dts: qcom: " Geert Uytterhoeven
@ 2026-03-05 9:33 ` Konrad Dybcio
2026-03-05 9:55 ` Geert Uytterhoeven
2026-03-24 14:56 ` (subset) " Frank Li
` (2 subsequent siblings)
10 siblings, 1 reply; 18+ messages in thread
From: Konrad Dybcio @ 2026-03-05 9:33 UTC (permalink / raw)
To: Geert Uytterhoeven, Marc Zyngier, Neil Armstrong, Kevin Hilman,
Jerome Brunet, Martin Blumenstingl, Peter Griffin,
André Draszik, Tudor Ambarus, Alim Akhtar, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel
On 3/4/26 6:10 PM, Geert Uytterhoeven wrote:
> Hi all,
>
> Unlike older GIC variants, the GICv3 DT bindings do not support
> specifying a CPU mask in PPI interrupt specifiers. Hence this patch
> series drop all such masks where they are still present.
I'm having trouble finding where that's used on pre-v3 even.. does
that actually get processed on the older iterations?
Konrad
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts
2026-03-05 9:33 ` [PATCH 0/7] arm64: dts: " Konrad Dybcio
@ 2026-03-05 9:55 ` Geert Uytterhoeven
2026-03-05 10:02 ` Konrad Dybcio
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2026-03-05 9:55 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Marc Zyngier, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, imx, linux-arm-msm,
linux-renesas-soc, linux-kernel
Hi Konrad,
On Thu, 5 Mar 2026 at 10:33, Konrad Dybcio
<konrad.dybcio@oss.qualcomm.com> wrote:
> On 3/4/26 6:10 PM, Geert Uytterhoeven wrote:
> > Unlike older GIC variants, the GICv3 DT bindings do not support
> > specifying a CPU mask in PPI interrupt specifiers. Hence this patch
> > series drop all such masks where they are still present.
>
> I'm having trouble finding where that's used on pre-v3 even.. does
> that actually get processed on the older iterations?
I had noticed the same, and had asked maz on IRC.
His answer:
"so far, we have never seen a GICv{1,2} system that didn't have all
of its PPIs
connected to the same set of devices."
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts
2026-03-05 9:55 ` Geert Uytterhoeven
@ 2026-03-05 10:02 ` Konrad Dybcio
2026-03-05 11:03 ` Marc Zyngier
0 siblings, 1 reply; 18+ messages in thread
From: Konrad Dybcio @ 2026-03-05 10:02 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Marc Zyngier, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, imx, linux-arm-msm,
linux-renesas-soc, linux-kernel
On 3/5/26 10:55 AM, Geert Uytterhoeven wrote:
> Hi Konrad,
>
> On Thu, 5 Mar 2026 at 10:33, Konrad Dybcio
> <konrad.dybcio@oss.qualcomm.com> wrote:
>> On 3/4/26 6:10 PM, Geert Uytterhoeven wrote:
>>> Unlike older GIC variants, the GICv3 DT bindings do not support
>>> specifying a CPU mask in PPI interrupt specifiers. Hence this patch
>>> series drop all such masks where they are still present.
>>
>> I'm having trouble finding where that's used on pre-v3 even.. does
>> that actually get processed on the older iterations?
>
> I had noticed the same, and had asked maz on IRC.
> His answer:
>
> "so far, we have never seen a GICv{1,2} system that didn't have all
> of its PPIs
> connected to the same set of devices."
lol, that's fun!
Konrad
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts
2026-03-05 10:02 ` Konrad Dybcio
@ 2026-03-05 11:03 ` Marc Zyngier
0 siblings, 0 replies; 18+ messages in thread
From: Marc Zyngier @ 2026-03-05 11:03 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Geert Uytterhoeven, Neil Armstrong, Kevin Hilman, Jerome Brunet,
Martin Blumenstingl, Peter Griffin, André Draszik,
Tudor Ambarus, Alim Akhtar, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding, linux-arm-kernel,
linux-amlogic, linux-samsung-soc, imx, linux-arm-msm,
linux-renesas-soc, linux-kernel
On Thu, 05 Mar 2026 10:02:01 +0000,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> wrote:
>
> On 3/5/26 10:55 AM, Geert Uytterhoeven wrote:
> > Hi Konrad,
> >
> > On Thu, 5 Mar 2026 at 10:33, Konrad Dybcio
> > <konrad.dybcio@oss.qualcomm.com> wrote:
> >> On 3/4/26 6:10 PM, Geert Uytterhoeven wrote:
> >>> Unlike older GIC variants, the GICv3 DT bindings do not support
> >>> specifying a CPU mask in PPI interrupt specifiers. Hence this patch
> >>> series drop all such masks where they are still present.
> >>
> >> I'm having trouble finding where that's used on pre-v3 even.. does
> >> that actually get processed on the older iterations?
> >
> > I had noticed the same, and had asked maz on IRC.
> > His answer:
> >
> > "so far, we have never seen a GICv{1,2} system that didn't have all
> > of its PPIs
> > connected to the same set of devices."
>
> lol, that's fun!
For some definition of fun. If you want to get a top-class headache,
have a look at what that means to handle a single INTID being routed
different drivers based on the *affinity* of the interrupt.
HW people who come up with these contraptions should be spanked
repeatedly and preferably asymmetrically.
N,
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: (subset) [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
` (7 preceding siblings ...)
2026-03-05 9:33 ` [PATCH 0/7] arm64: dts: " Konrad Dybcio
@ 2026-03-24 14:56 ` Frank Li
2026-03-26 3:19 ` Bjorn Andersson
2026-03-26 8:58 ` Neil Armstrong
10 siblings, 0 replies; 18+ messages in thread
From: Frank Li @ 2026-03-24 14:56 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Peter Griffin, André Draszik, Tudor Ambarus, Alim Akhtar,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding, Marc Zyngier,
Geert Uytterhoeven
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel
On Wed, 04 Mar 2026 18:10:57 +0100, Geert Uytterhoeven wrote:
> Hi all,
>
> Unlike older GIC variants, the GICv3 DT bindings do not support
> specifying a CPU mask in PPI interrupt specifiers. Hence this patch
> series drop all such masks where they are still present.
>
> This has been compile-tested only. But note that all such masks were
> removed before from Renesas SoCs in commit 8b6a006c914aac17 ("arm64:
> dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3
> systems")).
>
> [...]
Applied, thanks!
[3/7] arm64: dts: fsl-ls1028a: Drop CPU masks from GICv3 PPI interrupts
commit: 7348e8d71c593792df4ebf653d98a576c04c851c
[4/7] arm64: dts: freescale: imx: Drop CPU masks from GICv3 PPI interrupts
commit: f6c18c1c4ba574005d3b95faab0e8a3796cf3346
Best regards,
--
Frank Li <Frank.Li@nxp.com>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: (subset) [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
` (8 preceding siblings ...)
2026-03-24 14:56 ` (subset) " Frank Li
@ 2026-03-26 3:19 ` Bjorn Andersson
2026-03-26 8:58 ` Neil Armstrong
10 siblings, 0 replies; 18+ messages in thread
From: Bjorn Andersson @ 2026-03-26 3:19 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Peter Griffin, André Draszik, Tudor Ambarus, Alim Akhtar,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Dinh Nguyen, Konrad Dybcio, Thierry Reding, Marc Zyngier,
Geert Uytterhoeven
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel
On Wed, 04 Mar 2026 18:10:57 +0100, Geert Uytterhoeven wrote:
> Hi all,
>
> Unlike older GIC variants, the GICv3 DT bindings do not support
> specifying a CPU mask in PPI interrupt specifiers. Hence this patch
> series drop all such masks where they are still present.
>
> This has been compile-tested only. But note that all such masks were
> removed before from Renesas SoCs in commit 8b6a006c914aac17 ("arm64:
> dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3
> systems")).
>
> [...]
Applied, thanks!
[7/7] arm64: dts: qcom: Drop CPU masks from GICv3 PPI interrupts
commit: 99bb0693df91db9338fa69d496de4601c9582058
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: (subset) [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts
2026-03-04 17:10 [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Geert Uytterhoeven
` (9 preceding siblings ...)
2026-03-26 3:19 ` Bjorn Andersson
@ 2026-03-26 8:58 ` Neil Armstrong
10 siblings, 0 replies; 18+ messages in thread
From: Neil Armstrong @ 2026-03-26 8:58 UTC (permalink / raw)
To: Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Peter Griffin,
André Draszik, Tudor Ambarus, Alim Akhtar, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Dinh Nguyen,
Bjorn Andersson, Konrad Dybcio, Thierry Reding, Marc Zyngier,
Geert Uytterhoeven
Cc: linux-arm-kernel, linux-amlogic, linux-samsung-soc, imx,
linux-arm-msm, linux-renesas-soc, linux-kernel
Hi,
On Wed, 04 Mar 2026 18:10:57 +0100, Geert Uytterhoeven wrote:
> Hi all,
>
> Unlike older GIC variants, the GICv3 DT bindings do not support
> specifying a CPU mask in PPI interrupt specifiers. Hence this patch
> series drop all such masks where they are still present.
>
> This has been compile-tested only. But note that all such masks were
> removed before from Renesas SoCs in commit 8b6a006c914aac17 ("arm64:
> dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3
> systems")).
>
> [...]
Thanks, Applied to https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git (v7.1/arm64-dt)
[1/7] arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts
https://git.kernel.org/amlogic/c/ff6c02a40dc8706c0b13b3b12cfe228c38bb7857
These changes has been applied on the intermediate git tree [1].
The v7.1/arm64-dt branch will then be sent via a formal Pull Request to the Linux SoC maintainers
for inclusion in their intermediate git branches in order to be sent to Linus during
the next merge window, or sooner if it's a set of fixes.
In the cases of fixes, those will be merged in the current release candidate
kernel and as soon they appear on the Linux master branch they will be
backported to the previous Stable and Long-Stable kernels [2].
The intermediate git branches are merged daily in the linux-next tree [3],
people are encouraged testing these pre-release kernels and report issues on the
relevant mailing-lists.
If problems are discovered on those changes, please submit a signed-off-by revert
patch followed by a corrective changeset.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git
[2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
[3] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
--
Neil
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