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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id o5-20020ac24345000000b004f004c0498esm1879989lfl.71.2023.06.07.11.24.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Jun 2023 11:24:07 -0700 (PDT) Message-ID: Date: Wed, 7 Jun 2023 20:24:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Content-Language: en-US To: Varadarajan Narayanan , agross@kernel.org, andersson@kernel.org, vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, catalin.marinas@arm.com, will@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de, arnd@arndb.de, geert+renesas@glider.be, neil.armstrong@linaro.org, nfraprado@collabora.com, broonie@kernel.org, rafal@milecki.pl, quic_srichara@quicinc.com, quic_varada@quicinc.org, quic_wcheng@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org References: <1b48e737aa14f5b5539cbf04d473182121d5b1ad.1686126439.git.quic_varada@quicinc.com> From: Konrad Dybcio Subject: Re: [PATCH 7/9] arm64: dts: qcom: ipq5332: Add USB related nodes In-Reply-To: <1b48e737aa14f5b5539cbf04d473182121d5b1ad.1686126439.git.quic_varada@quicinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230607_112411_201519_708D1B57 X-CRM114-Status: GOOD ( 17.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7.06.2023 12:56, Varadarajan Narayanan wrote: > Add USB phy and controller nodes > > Signed-off-by: Varadarajan Narayanan > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 55 +++++++++++++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index c2d6cc65..3183357 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -383,6 +383,61 @@ > status = "disabled"; > }; > }; > + > + usb_0_m31phy: hs_m31phy@7b000 { > + compatible = "qcom,ipq5332-m31-usb-hsphy"; > + reg = <0x0007b000 0x12C>, random uppercase hex > + <0x08af8800 0x400>; > + reg-names = "m31usb_phy_base", > + "qscratch_base"; > + phy_type= "utmi"; Missing space before '=' > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > + reset-names = "usb2_phy_reset"; > + > + status = "okay"; If you're only defining the node, it's enabled by default In this case, you'd probably want to disable it by default. > + }; > + > + usb2: usb2@8a00000 { > + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; Please push these 3 properties to the end And add status = "disabled" below them. > + > + reg = <0x08af8800 0x100>; > + > + clocks = <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_SNOC_USB_CLK>, > + <&gcc GCC_USB0_SLEEP_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + Please remove this newline. > + clock-names = "core", > + "iface", > + "sleep", > + "mock_utmi"; Please align this, and all other similar lists. > + > + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; interrupts-extended is unnecessary with just a single interrupt source.. you can make it `interrupts` and drop the GIC reference. It would also be nice to push the interrupt properties below 'reg'. We're working on documenting and automating checking the preferred property order. > + interrupt-names = "pwr_event"; > + > + resets = <&gcc GCC_USB_BCR>; > + > + qcom,select-utmi-as-pipe-clk; > + > + usb2_0_dwc: usb@8a00000 { > + compatible = "snps,dwc3"; > + reg = <0x08a00000 0xe000>; > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "ref"; > + interrupts = ; > + usb-phy = <&usb_0_m31phy>; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + snps,ref-clock-period-ns = <21>; 1/21 is 0.0476.. that doesn't seem to correspond to the ref clk frequency? Konrad > + }; > + }; > }; > > timer { _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel