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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFz8d-0002jE-Rh; Wed, 09 Sep 2020 12:23:48 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kFz8Y-0002gZ-AY; Wed, 09 Sep 2020 12:23:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AD3B5113E; Wed, 9 Sep 2020 05:23:41 -0700 (PDT) Received: from [192.168.1.179] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8081D3F68F; Wed, 9 Sep 2020 05:23:40 -0700 (PDT) Subject: Re: [PATCH 3/5] drm/panfrost: add support for reset quirk To: Neil Armstrong , robh@kernel.org, tomeu.vizoso@collabora.com, alyssa.rosenzweig@collabora.com References: <20200908151853.4837-1-narmstrong@baylibre.com> <20200908151853.4837-4-narmstrong@baylibre.com> From: Steven Price Message-ID: Date: Wed, 9 Sep 2020 13:23:39 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200908151853.4837-4-narmstrong@baylibre.com> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200909_082342_414362_8C3D9E1A X-CRM114-Status: GOOD ( 25.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 08/09/2020 16:18, Neil Armstrong wrote: > The T820, G31 & G52 GPUs integratewd by Amlogic in the respective GXM, G12A/SM1 & G12B > SoCs needs a quirk in the PWR registers at the GPU reset time. > > This adds a callback in the device compatible struct of permit this. > > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/panfrost/panfrost_device.h | 3 +++ > drivers/gpu/drm/panfrost/panfrost_gpu.c | 4 ++++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h > index 2cf1a6a13af8..4c9cd5452ba5 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_device.h > +++ b/drivers/gpu/drm/panfrost/panfrost_device.h > @@ -73,6 +73,9 @@ struct panfrost_compatible { > > /* IOMMU quirks flags */ > unsigned long pgtbl_quirks; > + > + /* Vendor implementation quirks at reset time callback */ > + void (*vendor_reset_quirk)(struct panfrost_device *pfdev); > }; > > struct panfrost_device { > diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c > index e0f190e43813..c129aaf77790 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c > +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c > @@ -62,6 +62,10 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfdev) > gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); > gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); > > + /* The Amlogic GPU integration needs quirks at this stage */ > + if (pfdev->comp->vendor_reset_quirk) > + pfdev->comp->vendor_reset_quirk(pfdev); > + > ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, > val, val & GPU_IRQ_RESET_COMPLETED, 100, 10000); Placing the quirk before the reset has completed is dodgy. Can this be ordered after the GPU_IRQ_RESET_COMPLETED signal has been seen? The problem is the reset could (in theory) cause a power transition (e.g. if the GPU is reset while a core is powered) and changing the PWR_OVERRIDEx registers during a transition is undefined. But I don't know the details of how the hardware is broken so it is possible the override is needed for the reset to complete so this would need testing. I also wonder if this could live in panfrost_gpu_init_quirks() instead? Although that is mostly about quirks common to all Mali GPU implementations rather than a specific implementation. Although now I've looked I've noticed we have a bug as we don't appear to reapply those quirks after a reset - I'll send a patch! Steve _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel