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Wed, 20 Feb 2019 11:17:43 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 20 Feb 2019 11:17:43 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 20 Feb 2019 11:17:43 -0600 Received: from [172.22.219.123] (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1KHHc1Q030260; Wed, 20 Feb 2019 11:17:39 -0600 Subject: Re: [PATCH v5 05/10] dt-bindings: irqchip: Introduce TISCI Interrupt router bindings To: Tony Lindgren References: <4791de04-63af-4c5e-db9c-47634fcb8dc9@ti.com> <20190214154100.GB5720@atomide.com> <20190214174612.GF5720@atomide.com> <171e8597-2156-747d-d024-7b4bfc6f9186@ti.com> <20190215161629.GK5720@atomide.com> <2369739e-3bc8-257a-99e0-db2951c6777d@ti.com> <20190218143245.GC15711@atomide.com> <84b3ec21-9ce9-b9a8-80a9-75001db43a90@ti.com> <20190219153537.GJ15711@atomide.com> <20190220163651.GS15711@atomide.com> From: Lokesh Vutla Message-ID: Date: Wed, 20 Feb 2019 22:47:37 +0530 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0 MIME-Version: 1.0 In-Reply-To: <20190220163651.GS15711@atomide.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190220_091804_605741_92D995AA X-CRM114-Status: GOOD ( 19.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nishanth Menon , Device Tree Mailing List , jason@lakedaemon.net, marc.zyngier@arm.com, Tero Kristo , Linus Walleij , Sekhar Nori , linux-kernel@vger.kernel.org, Peter Ujfalusi , Rob Herring , Santosh Shilimkar , tglx@linutronix.de, Linux ARM Mailing List Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Tony, On 2/20/2019 10:06 PM, Tony Lindgren wrote: > Hi, > > Some more info on chained irq vs mux below that might > help. > > * Tony Lindgren [190219 15:36]: >> * Lokesh Vutla [190219 08:51]: >>> With this can you tell me how can we not have a device-tree and still support >>> irq allocation? >> >> Using standard dts reg property to differentiate the interrupt >> router instances. And if the interrupt router is a mux, you should >> treat it as a mux rather than a chained interrupt controller. >> >> We do have drivers/mux nowadays, not sure if it helps in this case >> as at least timer interrupts need to be configured very early. > > Adding Linus Walleij to Cc since he posted a good test to > consider if something should use chained (or nested) irq: > > "individual masking and ACKing bits and can all be used at the > same time" [0] Interrupt Router just routes M inputs to N outputs. One input can only be mapped to one output. This is a clear case of a hierarchical domain and the driver is implementing it. Thanks and regards, Lokesh > > Not sure if we have that documented somewhere? > > But seems like the interrupt router should be set up as > a separate mux driver talking with firmware that the > interrupt controller driver calls on request_irq(> > Cheers, > > Tony > > > [0] https://marc.info/?l=linux-omap&m=155065629529311&w=2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel