[PATCH] ARM: S5PV210: allow clk to use clksrc as parents

[s.nawrocki@samsung.com (Sylwester Nawrocki)]

Hello,

On Tue, 13 Jul 2010 13:21:54 +0900, Kukjin Kim wrote:

> MyungJoo Ham wrote:
>> 
>> 
>  (snip)
> 
[snip]
> 
> Basically, each clock which is used in each device driver such as lcd
> module clock, camemra module clock should be controlled in its device
> driver.
> 
> Let's say, in the case of camera module clock, FIMC IP has a specific
> divider which is used clock dividing for camera module clock. And the
> divider which is in FIMC IP has own rate for camera module at that time.
> So cannot/no need to define it in the common clock part such as clock.c.

IMO FIMC clock divider control registers are located in the clock 
controller IO memory, not in the FIMC IP. But possibly you meant 
something different than SCLK_CAM0/1 here.

So if we are considering SCLK_CAM0/1 the FIMC driver should be able to 
configure dividers corresponding to these clock outputs through the clk 
API. 
There is core clock multiplexer in FIMC IP in some SoCs though, so in 
general you are right, it would not be possible to control all clocks
with clk API as for now, since the dividers are located in specific IPs 
(e.g. SDHCI controller, FIMD).

Regards,
Sylwester

> 
> In other words, can't implement set_rate() or get_rate() for camera
> module clock in the common clock part, because FIMC IP block has own
> specific divider for it.
> 
> 
[snip]

> Thanks.
> 
> Best regards,
> Kgene.