From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF507C64E7A for ; Tue, 1 Dec 2020 16:05:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4F4B02222A for ; Tue, 1 Dec 2020 16:05:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="YkNzwWDl" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4F4B02222A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:In-reply-to:Subject:To: From:References:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cP7JMyPSrss/XFX6b/8lIq6N8RbvZXVCnWN/59jjoqs=; b=YkNzwWDltFTODRen8VsVKFQ0v ActxOQLEfS81XQO0BRTu56iAsa9RR2yeSJn5FCxdytrIHfsiipE2IL4tFtR3qsM9NGMIaOUNfsuWy YKwDH/v6AY3VRWZf8Vr5h5npfgImFMB6XpqhSa6opIGDJdwQl7X7A0NzwkfDXlk25wYLDWjTsfpP9 ApeLO3t6PyBj3oQRQ2vagWYUTExfqOz9kS6sMDHGakUCH0oTIw+Z2h8A/ucJOQJb4LcL7e27YauAE pFEJEdI7pRjo/UT8PcgRYPglo4Itoqe0+rMzdl7MOmqzmFHyMGgoJVWBofCCBuuKfRqvLtaIBxFA2 6fzOn+57A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kk88I-0007Ow-Ke; Tue, 01 Dec 2020 16:04:02 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kk88E-0007OJ-S6 for linux-arm-kernel@lists.infradead.org; Tue, 01 Dec 2020 16:04:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 71A2F101E; Tue, 1 Dec 2020 08:03:55 -0800 (PST) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B232E3F575; Tue, 1 Dec 2020 08:03:52 -0800 (PST) References: <20201201025944.18260-1-song.bao.hua@hisilicon.com> <20201201025944.18260-2-song.bao.hua@hisilicon.com> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: Barry Song Subject: Re: [RFC PATCH v2 1/2] topology: Represent clusters of CPUs within a die. In-reply-to: <20201201025944.18260-2-song.bao.hua@hisilicon.com> Date: Tue, 01 Dec 2020 16:03:46 +0000 Message-ID: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201201_110359_206403_83DA9E6F X-CRM114-Status: GOOD ( 14.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: juri.lelli@redhat.com, mark.rutland@arm.com, vincent.guittot@linaro.org, prime.zeng@hisilicon.com, peterz@infradead.org, catalin.marinas@arm.com, Jonathan.Cameron@huawei.com, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, rostedt@goodmis.org, linuxarm@huawei.com, bsegall@google.com, linux-acpi@vger.kernel.org, mingo@redhat.com, mgorman@suse.de, xuwei5@huawei.com, gregkh@linuxfoundation.org, will@kernel.org, dietmar.eggemann@arm.com, linux-arm-kernel@lists.infradead.org, lenb@kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 01/12/20 02:59, Barry Song wrote: > That means the cost to transfer ownership of a cacheline between CPUs > within a cluster is lower than between CPUs in different clusters on > the same die. Hence, it can make sense to tell the scheduler to use > the cache affinity of the cluster to make better decision on thread > migration. > > This patch simply exposes this information to userspace libraries > like hwloc by providing cluster_cpus and related sysfs attributes. > PoC of HWLOC support at [2]. > > Note this patch only handle the ACPI case. > AIUI this requires PPTT to describe your system like so: {Processor nodes} {Caches} [Node0] ----------------> [L3] ^ | [Cluster0] ---------------> [] ^ | [CPU0] ------------> [L1] -> [L2] which is a bit odd, because there is that middling level without any private resources. I suppose right now this is the only way to describe this kind of cache topology via PPTT, but is that widespread? Now, looking at the Ampere eMAG's PPTT, this has a "similar" shape. The topology is private L1, L2 shared by pairs of CPUs, shared L3 [1]. If I parse the PPTT thing right this is encoded as: {Processor nodes} {Caches} [Cluster0] -------------> ([L3] not present in my PPTT for some reason) ^ | [ Pair0 ] ------------> [L2] ^ ^ | | | [CPU1] ------------> [L1] [CPU0] -----------------> [L1] So you could spin the same story there were first scanning the pair and then the cluster could help. [1]: https://en.wikichip.org/wiki/ampere_computing/emag/8180 > Special consideration is needed for SMT processors, where it is > necessary to move 2 levels up the hierarchy from the leaf nodes > (thus skipping the processor core level). > > Currently the ID provided is the offset of the Processor > Hierarchy Nodes Structure within PPTT. Whilst this is unique > it is not terribly elegant so alternative suggestions welcome. > Skimming through the spec, this sounds like something the ID structure (Type 2) could be used for. However in v1 Jonathan and Sudeep talked about UID's / DSDT, any news on that? > Note that arm64 / ACPI does not provide any means of identifying > a die level in the topology but that may be unrelate to the cluster > level. > > [1] ACPI Specification 6.3 - section 5.2.29.1 processor hierarchy node > structure (Type 0) > [2] https://github.com/hisilicon/hwloc/tree/linux-cluster > > Signed-off-by: Jonathan Cameron > Signed-off-by: Barry Song _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel