From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D00CEC433E0 for ; Fri, 31 Jul 2020 00:10:37 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 985DE2076B for ; Fri, 31 Jul 2020 00:10:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="S32nX62h" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 985DE2076B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:In-reply-to:Subject:To: From:References:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=lxEPNB+6w0e3IC6s3ZA7cU+lP/aZtz5kG4z9FrfQt7g=; b=S32nX62hgrL11Y3b1fu6WYgsI pLXu7pvSxV+hih9JKdgBaqHIczOZ0suWsjbNFmaneCLCh+Pl4ToRPDHzid9AGQdb0TUviQxQVm0cI XU88Jy0WaxwB4VVtJae9ivV4A3h7153VKKazBheCpFT1PxvilUAgsMTzL+Vr//TiVX+AS/zoWWZkY CvXpb2p0h3lDARFyS/9rGKP2WHIiL5kaOlKVSqdOv5Q7wTJV+pCvNNM1StX7Q9ipF1ev3bgAthPZk +EhRfjtCbpUZDZbz7Apt2PvrizYNb0Ha6Y6RzUpylMULBN5gVC9i2fFuNFXriZAgObY3m2clxNRni Ybn2rDKEA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k1Iba-0000gq-M8; Fri, 31 Jul 2020 00:08:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k1IbY-0000gJ-Iz for linux-arm-kernel@lists.infradead.org; Fri, 31 Jul 2020 00:08:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8544731B; Thu, 30 Jul 2020 17:08:53 -0700 (PDT) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9EF0F3F66E; Thu, 30 Jul 2020 17:08:52 -0700 (PDT) References: <20200730170321.31228-1-valentin.schneider@arm.com> <20200730170321.31228-3-valentin.schneider@arm.com> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: Marc Zyngier Subject: Re: [PATCH v2 2/2] irqchip/gic-v2, v3: Prevent SW resends entirely In-reply-to: Date: Fri, 31 Jul 2020 01:08:47 +0100 Message-ID: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200730_200856_691966_E14FEC7A X-CRM114-Status: GOOD ( 22.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Gleixner , Lorenzo Pieralisi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jason Cooper Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 30/07/20 19:10, Marc Zyngier wrote: [...] >> diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c >> index e2b4cae88bce..a91ce1e73bd2 100644 >> --- a/drivers/irqchip/irq-gic.c >> +++ b/drivers/irqchip/irq-gic.c >> @@ -983,6 +983,7 @@ static int gic_irq_domain_map(struct irq_domain >> *d, unsigned int irq, >> irq_hw_number_t hw) >> { >> struct gic_chip_data *gic = d->host_data; >> + struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); >> >> if (hw < 32) { >> irq_set_percpu_devid(irq); >> @@ -992,8 +993,11 @@ static int gic_irq_domain_map(struct irq_domain >> *d, unsigned int irq, >> irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, >> handle_fasteoi_irq, NULL, NULL); >> irq_set_probe(irq); >> - irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); >> + irqd_set_single_target(irqd); >> } >> + >> + /* Prevents SW retriggers which mess up the ACK/EOI ordering */ >> + irqd_set_handle_enforce_irqctx(irqd); >> return 0; >> } > > I'm OK with this in principle, but this requires additional changes > in the rest of the GIC universe. The ITS driver needs to provide its own > retrigger function for LPIs (queuing an INT command), and any of the > SPI generating widgets that can be stacked on top of a GIC (GICv3-MBI, > GICv2m, and all the other Annapurna/Marvell/NVDIA wonders need to gain > directly or indirectly a call to irq_chip_retrigger_hierarchy(). > Eep, yes indeed... I didn't see that can was full of worms, though even if it only really matters for eoimode=0 I think it might still be worth it (if only to respect the spec). > We can probably avoid changing the MSI widgets by teaching the MSI > code about the HW retrigger, but a number of other non-MSI drivers > will need some help... > > I'll have a look tomorrow. > For LPIs AFAICT we could directly reuse its_irq_set_irqchip_state() - I see the VPE side of things already has a HW retrigger callback. For gicv2m, I *think* we'd want irq_chip_retrigger_hierarchy() on both MSI domains (which IIUC you suggest might be doable by adding the retrigger as a default MSI chip op). I'm not very familiar with the rest of the fauna, so I'll have to do some reading tomorrow as well; it's probably high time for me to actually read up on LPIs & ITS while I'm at it... > Thanks, > > M. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel