From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F123C433E0 for ; Thu, 2 Jul 2020 13:24:28 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DACDE20885 for ; Thu, 2 Jul 2020 13:24:27 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="l+RxtzXL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DACDE20885 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:In-reply-to:Subject:To: From:References:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=mNsVtHqn2Hrrd7qeEGtHYJQLX9NyFt+8AsXbsLf919k=; b=l+RxtzXLtG/O0eFoOX7ofx+wB LIMOdIwy1QZF0ffInD4Es/YTcjPZS3zYMQw9WVxnsgAqulHSVB7aKAGWd2cpVntFIOkVMvBhJr8i0 gD6LSdYxmH6OUbMJB+SZkbMBleAZMw5fw6EbBDruN/Fb2DaivaY8qs32vYYukPMxbAbmLfLqrhaLi LvoiRKIgUXOfU4VutXXXuRHu8oGSIsi+nG8qIzBw6OQ+2fFeozkGv7jRESwEKizLEhZfTbAhS0fWT F6imocrAfMNhBCp7/JXXUdNHcsMxnhoJIB9f2yWmvs2XnZgXtK9ThUUGVkzunnCkPd1+kN1Lnx6LR 4qGMz78Dg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqzBH-0004Au-G8; Thu, 02 Jul 2020 13:23:11 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jqzBF-0004AV-0N for linux-arm-kernel@lists.infradead.org; Thu, 02 Jul 2020 13:23:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0417B1FB; Thu, 2 Jul 2020 06:23:08 -0700 (PDT) Received: from e113632-lin (e113632-lin.cambridge.arm.com [10.1.194.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 55C1A3F68F; Thu, 2 Jul 2020 06:23:06 -0700 (PDT) References: <20200624195811.435857-1-maz@kernel.org> <20200624195811.435857-7-maz@kernel.org> User-agent: mu4e 0.9.17; emacs 26.3 From: Valentin Schneider To: Marc Zyngier Subject: Re: [PATCH v2 06/17] irqchip/gic-v3: Configure SGIs as standard interrupts In-reply-to: Date: Thu, 02 Jul 2020 14:23:04 +0100 Message-ID: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200702_092309_120504_B87FFEEF X-CRM114-Status: GOOD ( 13.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sumit Garg , Florian Fainelli , Russell King , Jason Cooper , kernel-team@android.com, Andrew Lunn , Catalin Marinas , Gregory Clement , linux-kernel@vger.kernel.org, Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 30/06/20 11:15, Marc Zyngier wrote: > On 2020-06-25 19:25, Valentin Schneider wrote: >> Also, while staring at this it dawned on me that IPI's don't need the >> eoimode=0 isb(): due to how the IPI flow-handler is structured, we'll >> get a >> gic_eoi_irq() just before calling into the irqaction. Dunno how much we >> care about it. > > That's interesting. This ISB is a leftover from the loop we had before > the pseudo-NMI code, where we had to make sure the write to EOIR was > ordered with the read from IAR. > > Given that we have an exception return right after the interrupt > handling, I *think* we could get rid of it (but that would need > mode checking on broken systems such as TX1...). I don't think > this is specific to IPIs though. > If I got this one right: 39a06b67c2c1 ("irqchip/gic: Ensure we have an ISB between ack and ->handle_irq") you're describing case 2, which is indeed gone on gic-v3. However IIUC we also want an ISB between poking IAR and calling into the irqaction (case 1) - we get just that with IPIs due to the early gic_eoi_irq(), but we don't for the other flows. > Thanks, > > M. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel