* Add support for the 16-way L310 L2 cache controller
[not found] <3756028016583358140@unknownmsgid>
@ 2010-04-30 17:17 ` Jason McMullan
0 siblings, 0 replies; 4+ messages in thread
From: Jason McMullan @ 2010-04-30 17:17 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Apr 29, 2010 at 12:20 PM, Will Deacon <will.deacon@arm.com> wrote:
> The patch entitled `Add support for the 16-way L310 L2 cache controller'
> which you submitted to RMK's patch system appears to perform a 16-way
> invalidation even when the ways might not be present. This results in
> writes to the reserved bits [15:8] of the invalidate-by-way ctrl register.
Good catch Will. I'll update it, and sent it to the list.
--
Jason S. McMullan
jaosn.mcmullan at netronome.com
^ permalink raw reply [flat|nested] 4+ messages in thread
[parent not found: <-5319252541413655868@unknownmsgid>]
* Add support for the 16-way L310 L2 cache controller
[not found] <-5319252541413655868@unknownmsgid>
@ 2010-05-03 16:48 ` Jason McMullan
0 siblings, 0 replies; 4+ messages in thread
From: Jason McMullan @ 2010-05-03 16:48 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Apr 29, 2010 at 12:20 PM, Will Deacon <will.deacon@arm.com> wrote:
> The patch entitled `Add support for the 16-way L310 L2 cache controller'
> which you submitted to RMK's patch system appears to perform a 16-way
> invalidation even when the ways might not be present. This results in
> writes to the reserved bits [15:8] of the invalidate-by-way ctrl register.
>
> You can check the associativity by reading bit 16 of the auxiliary ctrl
> register.
This issue was addressed in the patches I submitted to the l-a-k list on
Friday.
Please review those, and I will re-submit to the patch queue if they meet
your approval.
--
Jason McMullan
^ permalink raw reply [flat|nested] 4+ messages in thread
* Add support for the 16-way L310 L2 cache controller
@ 2010-04-29 16:20 Will Deacon
2010-04-29 18:28 ` Russell King - ARM Linux
0 siblings, 1 reply; 4+ messages in thread
From: Will Deacon @ 2010-04-29 16:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jason,
The patch entitled `Add support for the 16-way L310 L2 cache controller'
which you submitted to RMK's patch system appears to perform a 16-way
invalidation even when the ways might not be present. This results in
writes to the reserved bits [15:8] of the invalidate-by-way ctrl register.
You can check the associativity by reading bit 16 of the auxiliary ctrl
register.
Will
^ permalink raw reply [flat|nested] 4+ messages in thread
* Add support for the 16-way L310 L2 cache controller
2010-04-29 16:20 Will Deacon
@ 2010-04-29 18:28 ` Russell King - ARM Linux
0 siblings, 0 replies; 4+ messages in thread
From: Russell King - ARM Linux @ 2010-04-29 18:28 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Apr 29, 2010 at 05:20:35PM +0100, Will Deacon wrote:
> Hi Jason,
>
> The patch entitled `Add support for the 16-way L310 L2 cache controller'
> which you submitted to RMK's patch system appears to perform a 16-way
> invalidation even when the ways might not be present. This results in
> writes to the reserved bits [15:8] of the invalidate-by-way ctrl register.
>
> You can check the associativity by reading bit 16 of the auxiliary ctrl
> register.
I'll discard it then; seems it needs review on the mailing list.
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2010-05-03 16:48 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
[not found] <3756028016583358140@unknownmsgid>
2010-04-30 17:17 ` Add support for the 16-way L310 L2 cache controller Jason McMullan
[not found] <-5319252541413655868@unknownmsgid>
2010-05-03 16:48 ` Jason McMullan
2010-04-29 16:20 Will Deacon
2010-04-29 18:28 ` Russell King - ARM Linux
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).