Re: FYI: i.MX8MP ISP (RKISP1) MI registers corruption: resolved

["Krzysztof Hałasa" <khalasa@piap.pl>]

Hi Stefan et al,

BTW I've added Lucas Stach and Shawn Guo to "Cc" list.

The problem is the CPU core power supply voltage :-)

- while the reference manual specifies the max ISP and MEDIA clocks at
  500 MHz, the datasheets show this requires the "overdrive" mode =
  increased CPU power supply voltage. In "normal" mode the ISPs are
  limited to 400 MHz (there are other limits, too).

- I've tried lowering the clock rate after booting the systems (with
  a CCM register write), but it didn't fix the problem. I guess some
  reset logic is affected here, and the (lower) clock rate must be set
  right from the start, in the DT.

- anyway, lowering the frequencies of ISP and MEDIA root clocks fixes
  the ISP2 MI corruption. I'm currently investigating PMIC settings
  (both my Compulab and SolidRun modules use PCA9450C PMICs), so perhaps
  I'll be able to use the higher 500 MHz clocks. It doesn't matter much,
  though.

- the question is if we should lower the clocks in the main imx8mp.dtsi
  DT file, or the overdrive mode should stay there, and the changes
  should be made to the individual board files, or maybe the U-Boot
  configs (PMIC output voltages) should be changed etc.
-- 
Krzysztof "Chris" HaBasa

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