[PATCH] ARM: perf_event: support dual-core with single PMU IRQ

[PATCH] ARM: perf_event: support dual-core with single PMU IRQ

[Rabin Vincent]

DB8500 (dual-core) has the PMU interrupts of both cores ORed into one.  Support
this by setting the affinity of the interrupt to the other core when the
current core finds that its counter has not overflowed when an interrupt
occurred.

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
---
 arch/arm/kernel/perf_event.c |   33 ++++++++++++++++++++++++++++++++-
 1 files changed, 32 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 5efa264..d07990e 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -377,9 +377,27 @@ validate_group(struct perf_event *event)
 	return 0;
 }

+static irqreturn_t armpmu_bounce_interrupt(int irq, void *dev)
+{
+	irqreturn_t ret = armpmu->handle_irq(irq, dev);
+
+	if (ret == IRQ_NONE) {
+		int other = !smp_processor_id();
+		irq_set_affinity(irq, cpumask_of(other));
+	}
+
+	/*
+	 * We should be able to get away with the amount of IRQ_NONEs we give,
+	 * while still having the spurious IRQ detection code kick in if the
+	 * interrupt really starts hitting spuriously.
+	 */
+	return ret;
+}
+
 static int
 armpmu_reserve_hardware(void)
 {
+	irq_handler_t irq_handler = armpmu->handle_irq;
 	int i, err = -ENODEV, irq;

 	pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
@@ -395,12 +413,25 @@ armpmu_reserve_hardware(void)
 		return -ENODEV;
 	}

+	/*
+	 * Some SoCs have the PMU IRQ lines of two cores wired together into a
+	 * single interrupt.
+	 */
+	if (pmu_device->num_resources < num_online_cpus()) {
+		if (num_online_cpus() > 2) {
+			pr_err(">2 cpus not supported for single-irq workaround");
+			return -ENODEV;
+		}
+
+		irq_handler = armpmu_bounce_interrupt;
+	}
+
 	for (i = 0; i < pmu_device->num_resources; ++i) {
 		irq = platform_get_irq(pmu_device, i);
 		if (irq < 0)
 			continue;

-		err = request_irq(irq, armpmu->handle_irq,
+		err = request_irq(irq, irq_handler,
 				  IRQF_DISABLED | IRQF_NOBALANCING,
 				  "armpmu", NULL);
 		if (err) {

--001636c5aa55c3c736049baacb0b
Content-Type: application/octet-stream; 
	name="0001-ARM-perf_event-support-dual-core-with-single-PMU-IRQ.patch"
Content-Disposition: attachment; 
	filename="0001-ARM-perf_event-support-dual-core-with-single-PMU-IRQ.patch"
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--001636c5aa55c3c736049baacb0b--

[PATCH] ARM: perf_event: support dual-core with single PMU IRQ

[Rabin Vincent]

DB8500 (dual-core) has the PMU interrupts of both cores ORed into one.  Sup=
port
this by keeping the interrupt directed at Core0 and IPIing Core1 when Core0
receives the interrupt and finds that its counter has not overflowed.

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
---
 arch/arm/kernel/perf_event.c |   48 ++++++++++++++++++++++++++++++++++++++=
+++-
 1 files changed, 47 insertions(+), 1 deletions(-)

diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 5efa264..a97e50f 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/uaccess.h>
+#include <linux/smp.h>

 #include <asm/cputype.h>
 #include <asm/irq.h>
@@ -377,9 +378,40 @@ validate_group(struct perf_event *event)
 	return 0;
 }

+static irqreturn_t armpmu_core2_irqret;
+
+/* Called via IPI on the second core */
+static void armpmu_kick(void *data)
+{
+	int irq =3D (int) data;
+
+	armpmu_core2_irqret =3D armpmu->handle_irq(irq, NULL);
+	smp_wmb();
+}
+
+static irqreturn_t armpmu_single_interrupt(int irq, void *dev)
+{
+	irqreturn_t irqret =3D armpmu->handle_irq(irq, dev);
+	int err;
+
+	if (irqret !=3D IRQ_NONE)
+		return irqret;
+
+	local_irq_enable();
+	err =3D smp_call_function_single(1, armpmu_kick, (void *) irq, true);
+	local_irq_disable();
+
+	if (err)
+		return irqret;
+
+	smp_rmb();
+	return armpmu_core2_irqret;
+}
+
 static int
 armpmu_reserve_hardware(void)
 {
+	irq_handler_t irq_handler =3D armpmu->handle_irq;
 	int i, err =3D -ENODEV, irq;

 	pmu_device =3D reserve_pmu(ARM_PMU_DEVICE_CPU);
@@ -395,12 +427,26 @@ armpmu_reserve_hardware(void)
 		return -ENODEV;
 	}

+	/*
+	 * Some SoCs have the PMU IRQ lines of two cores wired together into a
+	 * single interrupt.  Support these by poking the second core with an
+	 * IPI when its counters overflow.
+	 */
+	if (pmu_device->num_resources < num_online_cpus()) {
+		if (num_online_cpus() > 2) {
+			pr_err(">2 cpus not supported for single-irq workaround");
+			return -ENODEV;
+		}
+
+		irq_handler =3D armpmu_single_interrupt;
+	}
+
 	for (i =3D 0; i < pmu_device->num_resources; ++i) {
 		irq =3D platform_get_irq(pmu_device, i);
 		if (irq < 0)
 			continue;

-		err =3D request_irq(irq, armpmu->handle_irq,
+		err =3D request_irq(irq, irq_handler,
 				  IRQF_DISABLED | IRQF_NOBALANCING,
 				  "armpmu", NULL);
 		if (err) {
--=20
1.7.2.dirty

--0016e6d7efd7e78534049baae5b4
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	name="0001-ARM-perf_event-support-dual-core-with-single-PMU-IRQ.patch"
Content-Disposition: attachment; 
	filename="0001-ARM-perf_event-support-dual-core-with-single-PMU-IRQ.patch"
Content-Transfer-Encoding: base64
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