[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Tony Lindgren]

Use SMP and UP macros for cacheflush. Note that __flush_icache_all
currently won't work properly on ARMv7 SMP if support for ARMv6 is
compiled in.

Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm/include/asm/cacheflush.h |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..09a893e 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -16,6 +16,7 @@
 #include <asm/shmparam.h>
 #include <asm/cachetype.h>
 #include <asm/outercache.h>
+#include <asm/smp_plat.h>
 
 #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 
@@ -372,8 +373,10 @@ static inline void __flush_icache_all(void)
 	extern void v6_icache_inval_all(void);
 	v6_icache_inval_all();
 #elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
+	asm(								\
+	SMP(mcr	p15, 0, %0, c7, c1, 0	@ inv I-cache inner shareable)	\
+	UP(mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache)		\
+	    :								\
 	    : "r" (0));
 #else
 	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-- 
1.7.1

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 16:44]:
> On Tue, Aug 17, 2010 at 01:53:12PM +0300, Tony Lindgren wrote:
> > Here are some experimental patches to allow booting ARMv7 SMP
> > kernel on UP to some extent. Posting these early in case it is
> > of any help as I know at least Bryan Wu is working on similar
> > issues.
> 
> I think these are compeltely the wrong direction.  First thing to realise
> is that XIP in the "SMP and UP in one kernel" is not really practical -
> I'm not sure that many people who want that kind of flexibility also want
> XIP too.
> 
> So let's forget about the kernel text being read-only.

OK, at least for me.
 
> The second thing to realise is that most of the SMP dependencies are in
> assembly - and we can make lists of instructions and their modified
> versions that would be necessary to boot a SMP kernel on UP.

OK cool.
 
> So something like this will do (though note that not everywhere has been
> fixed up - such as the page table flags - or this patch tested yet.)

Great, will give it a try hopefully tomorrow. Sounds like that's the way
to deal with fixing up things when booting up older UP ARMv6 without the
32v6 support :)
 
> If we don't want the SMP-on-UP support for SMP kernels (it's not actually
> all that big - around 512 bytes) then we can discard the .smpalt.init
> section and the __fixup_smp code.

OK

Regards,

Tony

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
> Great, will give it a try hopefully tomorrow. Sounds like that's the way
> to deal with fixing up things when booting up older UP ARMv6 without the
> 32v6 support :)

What I've also been debating about is adding another word to the
smpalt structure, that being a set of flags which denote the situation
where the alternative should be used.

That means we can use it to do individual word replacements for SMP vs
UP, ARMv6 vs ARMv6k etc.

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 18:33]:
> On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
> > Great, will give it a try hopefully tomorrow. Sounds like that's the way
> > to deal with fixing up things when booting up older UP ARMv6 without the
> > 32v6 support :)
> 
> What I've also been debating about is adding another word to the
> smpalt structure, that being a set of flags which denote the situation
> where the alternative should be used.
> 
> That means we can use it to do individual word replacements for SMP vs
> UP, ARMv6 vs ARMv6k etc.

Sounds good to me. Maybe it should then be called cpualt instead of smpalt?

Tried booting your patch and needed the following fix for Cortex-A8 UP.

Now it boots to the following error:

Machine configuration botched (nr -1073741824), unable to continue.

Does some struct size need to be changed or something?

Regards,

Tony
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[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Bryan Wu]

On 08/19/2010 03:38 PM, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 18:33]:
>> On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
>>> Great, will give it a try hopefully tomorrow. Sounds like that's the way
>>> to deal with fixing up things when booting up older UP ARMv6 without the
>>> 32v6 support :)
>>
>> What I've also been debating about is adding another word to the
>> smpalt structure, that being a set of flags which denote the situation
>> where the alternative should be used.
>>
>> That means we can use it to do individual word replacements for SMP vs
>> UP, ARMv6 vs ARMv6k etc.
> 
> Sounds good to me. Maybe it should then be called cpualt instead of smpalt?
> 
> Tried booting your patch and needed the following fix for Cortex-A8 UP.
> 
> Now it boots to the following error:
> 
> Machine configuration botched (nr -1073741824), unable to continue.
> 
> Does some struct size need to be changed or something?
> 

I also tested these 2 patches on my beagle board based on -for-next branch for
linux-omap tree. I don't have debug hardware to find the kernel boot failure. It
looks like it stops at very early stage.

Do you know where is the message (nr -1073741824) coming from?

Thanks,
-- 
Bryan Wu <bryan.wu@canonical.com>
Kernel Developer    +86.138-1617-6545 Mobile
Ubuntu Kernel Team | Hardware Enablement Team
Canonical Ltd.      www.canonical.com
Ubuntu - Linux for human beings | www.ubuntu.com

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Bryan Wu <bryan.wu@canonical.com> [100819 12:31]:
> On 08/19/2010 03:38 PM, Tony Lindgren wrote:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100817 18:33]:
> >> On Tue, Aug 17, 2010 at 05:12:11PM +0300, Tony Lindgren wrote:
> >>> Great, will give it a try hopefully tomorrow. Sounds like that's the way
> >>> to deal with fixing up things when booting up older UP ARMv6 without the
> >>> 32v6 support :)
> >>
> >> What I've also been debating about is adding another word to the
> >> smpalt structure, that being a set of flags which denote the situation
> >> where the alternative should be used.
> >>
> >> That means we can use it to do individual word replacements for SMP vs
> >> UP, ARMv6 vs ARMv6k etc.
> > 
> > Sounds good to me. Maybe it should then be called cpualt instead of smpalt?
> > 
> > Tried booting your patch and needed the following fix for Cortex-A8 UP.
> > 
> > Now it boots to the following error:
> > 
> > Machine configuration botched (nr -1073741824), unable to continue.
> > 
> > Does some struct size need to be changed or something?
> > 
> 
> I also tested these 2 patches on my beagle board based on -for-next branch for
> linux-omap tree. I don't have debug hardware to find the kernel boot failure. It
> looks like it stops at very early stage.
> 
> Do you know where is the message (nr -1073741824) coming from?

Looks like something is not quite right with smp_on_up part of __fixup_smp,
returning early before smp_on_up does not produce that.

Regards,

Tony

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> Looks like something is not quite right with smp_on_up part of __fixup_smp,
> returning early before smp_on_up does not produce that.

It's probably overwriting some register it shouldn't be.  I might be
able to look at this sometime during the coming week... assuming that
the weather is as bad as they forecast and I have 'net connectivity.

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > returning early before smp_on_up does not produce that.
> 
> It's probably overwriting some register it shouldn't be.  I might be
> able to look at this sometime during the coming week... assuming that
> the weather is as bad as they forecast and I have 'net connectivity.

OK, I'll be offline too probably until late next week.

Tony

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [100820 04:59]:
> * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > returning early before smp_on_up does not produce that.
> > 
> > It's probably overwriting some register it shouldn't be.  I might be
> > able to look at this sometime during the coming week... assuming that
> > the weather is as bad as they forecast and I have 'net connectivity.

This seems to fix it.

Tony
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[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Russell King - ARM Linux]

On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [100820 04:59]:
> > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > > returning early before smp_on_up does not produce that.
> > > 
> > > It's probably overwriting some register it shouldn't be.  I might be
> > > able to look at this sometime during the coming week... assuming that
> > > the weather is as bad as they forecast and I have 'net connectivity.
> 
> This seems to fix it.

Thanks, merged that into my original patch - so here it is again with
everything updated.

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9295110..725a463 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1166,6 +1166,18 @@ config SMP
 
 	  If you don't know what to do here, say N.
 
+config SMP_ON_UP
+	bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
+	depends on SMP && !XIP
+	default y
+	help
+	  SMP kernels contain instructions which fail on non-SMP processors.
+	  Enabling this option allows the kernel to modify itself to make
+	  these instructions safe.  Disabling it allows about 1K of space
+	  savings.
+
+	  If you don' tknow what to do here, say Y.
+
 config HAVE_ARM_SCU
 	bool
 	depends on SMP
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..55974d2 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,32 @@
 	.long	9999b,9001f;			\
 	.popsection
 
+#ifdef CONFIG_SMP
+#define SMP(instr...)						\
+9998:	instr
+#define UP(instr...)						\
+	.pushsection ".smpalt.init", "a"			;\
+	.word	9998b						;\
+	instr							;\
+	.popsection
+#else
+#define SMP(instr...)
+#define UP(instr...) instr
+#endif
+
 /*
  * SMP data memory barrier
  */
 	.macro	smp_dmb
 #ifdef CONFIG_SMP
 #if __LINUX_ARM_ARCH__ >= 7
-	dmb
+	SMP(dmb)
 #elif __LINUX_ARM_ARCH__ == 6
-	mcr	p15, 0, r0, c7, c10, 5	@ dmb
+	SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
+#else
+#error Incompatible SMP platform
 #endif
+	UP(nop)
 #endif
 	.endm
 
diff --git a/arch/arm/include/asm/smp_midr.h b/arch/arm/include/asm/smp_midr.h
index e69de29..4538ba4 100644
--- a/arch/arm/include/asm/smp_midr.h
+++ b/arch/arm/include/asm/smp_midr.h
@@ -0,0 +1,17 @@
+#ifndef ASMARM_SMP_MIDR_H
+#define ASMARM_SMP_MIDR_H
+
+#define hard_smp_processor_id()						\
+	({								\
+		unsigned int cpunum;					\
+		__asm__("\n"						\
+			"1:	mrc p15, 0, %0, c0, c0, 5\n"		\
+			"	.pushsection \".smpalt.init\", \"a\"\n"	\
+			"	.word	1b\n"				\
+			"	mov	%0, #0\n"			\
+			"	.popsection"				\
+			: "=r" (cpunum));				\
+		cpunum &= 0x0F;						\
+	})
+
+#endif
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546a..1fd0db9 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
 #undef _TLB
 #undef MULTI_TLB
 
+#ifdef CONFIG_SMP_ON_UP
+#define MULTI_TLB 1
+#endif
+
 #define v3_tlb_flags	(TLB_V3_FULL | TLB_V3_PAGE)
 
 #ifdef CONFIG_CPU_TLB_V3
@@ -185,12 +189,15 @@
 # define v6wbi_always_flags	(-1UL)
 #endif
 
-#ifdef CONFIG_SMP
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
+#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
 			 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
-#else
-#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
+#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \
 			 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
+
+#ifdef CONFIG_SMP
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_smp
+#else
+#define v7wbi_tlb_flags	v7wbi_tlb_flags_up
 #endif
 
 #ifdef CONFIG_CPU_TLB_V7
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a..bb2ef60 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -965,11 +965,8 @@ kuser_cmpxchg_fixup:
 	beq	1b
 	rsbs	r0, r3, #0
 	/* beware -- each __kuser slot must be 8 instructions max */
-#ifdef CONFIG_SMP
-	b	__kuser_memory_barrier
-#else
-	usr_ret	lr
-#endif
+	SMP(b	__kuser_memory_barrier)
+	UP(usr_ret	lr)
 
 #endif
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..cf76484 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -86,6 +86,9 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+#ifdef CONFIG_SMP_ON_UP
+	bl	__fixup_smp
+#endif
 	bl	__create_page_tables
 
 	/*
@@ -333,4 +336,35 @@ __create_page_tables:
 ENDPROC(__create_page_tables)
 	.ltorg
 
+#ifdef CONFIG_SMP_ON_UP
+__fixup_smp:
+	and	r0, r9, #0xff000000
+	teq	r0, #0x41000000		@ ARM CPU?
+	bne	smp_on_up		@ no, assume UP
+	and	r0, r9, #0x00070000
+	teq	r0, #0x00070000		@ ARMv6/v7?
+	bne	smp_on_up		@ no, assume UP
+	mrc	p15, 0, r0, c0, c0, 5	@ read MIDR
+	movs	r0, r0, lsr #30
+	teqne	r0, #3			@ check top two bits 00 or 11
+	movne	pc, lr
+
+smp_on_up:
+	adr	r0, 1f
+	ldmia	r0, {r3, r6, r7}
+	sub	r3, r0, r3
+	add	r6, r6, r3
+	add	r7, r7, r3
+2:	cmp	r6, r7
+	ldmia	r6!, {r0, r4}
+	movhs	pc, lr
+	str	r4, [r0, r3]
+	b	2b
+ENDPROC(__fixup_smp)
+
+1:	.word	.
+	.word	__smpalt_begin
+	.word	__smpalt_end
+#endif
+
 #include "head-common.S"
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..53cb57e 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -40,6 +40,11 @@ SECTIONS
 		__tagtable_begin = .;
 			*(.taglist.init)
 		__tagtable_end = .;
+#ifdef CONFIG_SMP_ON_UP
+		__smpalt_begin = .;
+			*(.smpalt.init)
+		__smpalt_end = .;
+#endif
 
 		INIT_SETUP(16)
 
@@ -237,6 +242,12 @@ SECTIONS
 
 	/* Default discards */
 	DISCARDS
+
+#ifndef CONFIG_SMP_ON_UP
+	/DISCARD/ {
+		*(.smpalt.init)
+	}
+#endif
 }
 
 /*
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892..833ee85 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba..1b8b637 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
 #define ASM_ARCH_SMP_H __FILE__
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 extern void __iomem *gic_cpu_base_addr;
 
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x03;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab..d5c4030 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
 #ifndef ASMARM_ARCH_SMP_H
 #define ASMARM_ARCH_SMP_H
 
-
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc..87a9cf3 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
 #define ASMARM_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* This is required to wakeup the secondary core */
 extern void u8500_secondary_startup(void);
 
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 /*
  * We use IRQ1 as the IPI
  */
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621..e02bc7d 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
 #define __MACH_SMP_H
 
 #include <asm/hardware/gic.h>
-
-#define hard_smp_processor_id()				\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
+#include <asm/smp_midr.h>
 
 /*
  * We use IRQ1 as the IPI
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157..2aa59d5 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -91,11 +91,8 @@ ENTRY(v7_flush_kern_cache_all)
  THUMB(	stmfd	sp!, {r4-r7, r9-r11, lr}	)
 	bl	v7_flush_dcache_all
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 0		@ invalidate I-cache inner shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 0)		@ invalidate I-cache inner shareable
+	UP(mcr	p15, 0, r0, c7, c5, 0)		@ I+BTB cache invalidate
  ARM(	ldmfd	sp!, {r4-r5, r7, r9-r11, lr}	)
  THUMB(	ldmfd	sp!, {r4-r7, r9-r11, lr}	)
 	mov	pc, lr
@@ -171,11 +168,8 @@ ENTRY(v7_coherent_user_range)
 	cmp	r0, r1
 	blo	1b
 	mov	r0, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c7, c1, 6		@ invalidate BTB Inner Shareable
-#else
-	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB
-#endif
+	SMP(mcr	p15, 0, r0, c7, c1, 6)		@ invalidate BTB Inner Shareable
+	UP(mcr	p15, 0, r0, c7, c5, 6)		@ invalidate BTB
 	dsb
 	isb
 	mov	pc, lr
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac85..00692b0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
 #define TTB_RGN_WT	(2 << 3)
 #define TTB_RGN_WB	(3 << 3)
 
-#ifndef CONFIG_SMP
-#define TTB_FLAGS	TTB_RGN_WBWA
-#define PMD_FLAGS	PMD_SECT_WB
-#else
-#define TTB_FLAGS	TTB_RGN_WBWA|TTB_S
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_UP	TTB_RGN_WBWA
+#define PMD_FLAGS_UP	PMD_SECT_WB
+#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v6_proc_init)
 	mov	pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
 	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
@@ -156,9 +154,11 @@ cpu_pj4_name:
  */
 __v6_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1		@ Enable SMP/nAMP mode
+	SMP(mrc	p15, 0, r0, c1, c0, 1)		@ Enable SMP/nAMP mode
+	UP(nop)
 	orr	r0, r0, #0x20
-	mcr	p15, 0, r0, c1, c0, 1
+	SMP(mcr	p15, 0, r0, c1, c0, 1)
+	UP(nop)
 #endif
 
 	mov	r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 #endif /* CONFIG_MMU */
 	adr	r5, v6_crval
@@ -225,10 +226,16 @@ cpu_elf_name:
 __v6_proc_info:
 	.long	0x0007b000
 	.long	0x0007f000
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
@@ -249,10 +256,16 @@ __v6_proc_info:
 __pj4_v6_proc_info:
 	.long	0x560f5810
 	.long	0xff0ffff0
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d..07fc660 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
 #define TTB_IRGN_WT	((1 << 0) | (0 << 6))
 #define TTB_IRGN_WB	((1 << 0) | (1 << 6))
 
-#ifndef CONFIG_SMP
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
-#define PMD_FLAGS	PMD_SECT_WB
-#else
+#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
+#define PMD_FLAGS_UP	PMD_SECT_WB
+
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
-#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
-#endif
+#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
 
 ENTRY(cpu_v7_proc_init)
 	mov	pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
 	mov	r2, #0
 	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
-	orr	r0, r0, #TTB_FLAGS
+	SMP(orr	r0, r0, #TTB_FLAGS_SMP)
+	UP(orr	r0, r0, #TTB_FLAGS_UP)
 #ifdef CONFIG_ARM_ERRATA_430973
 	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
 #endif
@@ -188,7 +187,8 @@ cpu_v7_name:
  */
 __v7_setup:
 #ifdef CONFIG_SMP
-	mrc	p15, 0, r0, c1, c0, 1
+	SMP(mrc	p15, 0, r0, c1, c0, 1)
+	UP(mov	r0, #(1 << 6))			@ fake it for UP
 	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
 	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
 	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
@@ -235,7 +235,8 @@ __v7_setup:
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
-	orr	r4, r4, #TTB_FLAGS
+	SMP(orr	r4, r4, #TTB_FLAGS_SMP)
+	UP(orr	r4, r4, #TTB_FLAGS_UP)
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
 	mov	r10, #0x1f			@ domains 0, 1 = manager
 	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
@@ -330,10 +331,16 @@ cpu_elf_name:
 __v7_proc_info:
 	.long	0x000f0000		@ Required ID value
 	.long	0x000f0000		@ Mask for ID
-	.long   PMD_TYPE_SECT | \
+	SMP(.long \
+		PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ | \
+		PMD_FLAGS_SMP)
+	UP(.long \
+		PMD_TYPE_SECT | \
 		PMD_SECT_AP_WRITE | \
 		PMD_SECT_AP_READ | \
-		PMD_FLAGS
+		PMD_FLAGS_UP)
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_XN | \
 		PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a..26247c9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
  */
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
 #include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
 	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable) 
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable) 
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
+
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	ip, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, ip, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, ip, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, ip, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, ip, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	mov	pc, lr
 ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
 	mov	r0, r0, lsl #PAGE_SHIFT
 	mov	r1, r1, lsl #PAGE_SHIFT
 1:
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r0, c8, c3, 1		@ TLB invalidate U MVA (shareable)
-#else
-	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate U MVA
-#endif
+	SMP(mcr	p15, 0, r0, c8, c3, 1)		@ TLB invalidate U MVA (shareable)
+	UP(mcr	p15, 0, r0, c8, c7, 1)		@ TLB invalidate U MVA
 	add	r0, r0, #PAGE_SZ
 	cmp	r0, r1
 	blo	1b
 	mov	r2, #0
-#ifdef CONFIG_SMP
-	mcr	p15, 0, r2, c7, c1, 6		@ flush BTAC/BTB Inner Shareable
-#else
-	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
-#endif
+	SMP(mcr	p15, 0, r2, c7, c1, 6)		@ flush BTAC/BTB Inner Shareable
+	UP(mcr	p15, 0, r2, c7, c5, 6)		@ flush BTAC/BTB
 	dsb
 	isb
 	mov	pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
 ENTRY(v7wbi_tlb_fns)
 	.long	v7wbi_flush_user_tlb_range
 	.long	v7wbi_flush_kern_tlb_range
-	.long	v7wbi_tlb_flags
+	SMP(.long	v7wbi_tlb_flags_smp)
+	UP(.long	v7wbi_tlb_flags_up)
 	.size	v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 6a3ff65..ed96907 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
 #define OMAP_ARCH_SMP_H
 
 #include <asm/hardware/gic.h>
+#include <asm/smp_midr.h>
 
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
 	gic_raise_softirq(mask, 1);
 }
 
-/*
- * Read MPIDR: Multiprocessor affinity register
- */
-#define hard_smp_processor_id()			\
-	({						\
-		unsigned int cpunum;			\
-		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
-			: "=r" (cpunum));		\
-		cpunum &= 0x0F;				\
-	})
-
 #endif

[PATCH 0/4] Hacks to allow booting ARM SMP kernel on UP ARMv7

[Tony Lindgren]

* Russell King - ARM Linux <linux@arm.linux.org.uk> [100902 06:29]:
> On Mon, Aug 30, 2010 at 03:55:27PM -0700, Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [100820 04:59]:
> > > * Russell King - ARM Linux <linux@arm.linux.org.uk> [100819 13:13]:
> > > > On Thu, Aug 19, 2010 at 12:57:06PM +0300, Tony Lindgren wrote:
> > > > > Looks like something is not quite right with smp_on_up part of __fixup_smp,
> > > > > returning early before smp_on_up does not produce that.
> > > > 
> > > > It's probably overwriting some register it shouldn't be.  I might be
> > > > able to look at this sometime during the coming week... assuming that
> > > > the weather is as bad as they forecast and I have 'net connectivity.
> > 
> > This seems to fix it.
> 
> Thanks, merged that into my original patch - so here it is again with
> everything updated.

Your patch sure makes things simpler! The problem still is the
V6 vs V7 SMP code though.

Will post my six patches that apply on top of your patch as a reply to
this mail. With those, everything seems to work, at least after testing
on omap3630 (Cortex-A8 UP) and omap4430 (Cortex-A9 SMP).

Will, maybe see if there are some parts in your patchset that should
be used instead? I noticed pretty much all the earlier hacks are no
longer needed :)

Regards,

Tony

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Tony Lindgren]

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Shilimkar, Santosh]

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Thursday, September 02, 2010 9:50 PM
> To: Russell King - ARM Linux
> Cc: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Bryan Wu; Will Deacon
> Subject: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush
> 
> From 16c866489613ef8ea9d28ecf861f5a7ff4d60377 Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony@atomide.com>
> Date: Thu, 2 Sep 2010 08:20:02 -0700
> Subject: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush
> 
> Use SMP and UP macros for cacheflush. Note that __flush_icache_all
> currently won't work properly on ARMv7 SMP if support for ARMv6 is
> compiled in.
> 
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  arch/arm/include/asm/cacheflush.h |    7 +++++--
>  1 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/cacheflush.h
> b/arch/arm/include/asm/cacheflush.h
> index 4656a24..09a893e 100644
> --- a/arch/arm/include/asm/cacheflush.h
> +++ b/arch/arm/include/asm/cacheflush.h
> @@ -16,6 +16,7 @@
>  #include <asm/shmparam.h>
>  #include <asm/cachetype.h>
>  #include <asm/outercache.h>
> +#include <asm/smp_plat.h>
> 
>  #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
> 
> @@ -372,8 +373,10 @@ static inline void __flush_icache_all(void)
>  	extern void v6_icache_inval_all(void);
>  	v6_icache_inval_all();
>  #elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
> -	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner
> shareable\n"
> -	    :
> +	asm(								\
> +	SMP(mcr	p15, 0, %0, c7, c1, 0	@ inv I-cache inner shareable)
> 	\
> +	UP(mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache)		\
> +	    :								\
>  	    : "r" (0));
>  #else
>  	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"

Since UP/SMP both cases are handled, the above patch can be something like this now... 

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 9792a71..ebdff42 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -16,6 +16,7 @@
 #include <asm/shmparam.h>
 #include <asm/cachetype.h>
 #include <asm/outercache.h>
+#include <asm/smp_plat.h>
 
 #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 
@@ -394,13 +395,11 @@ static inline void __flush_icache_all(void)
 #ifdef CONFIG_ARM_ERRATA_411920
 	extern void v6_icache_inval_all(void);
 	v6_icache_inval_all();
-#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
-	asm("mcr	p15, 0, %0, c7, c1, 0	@ invalidate I-cache inner shareable\n"
-	    :
-	    : "r" (0));
 #else
-	asm("mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache\n"
-	    :
+	asm(								\
+	SMP(mcr	p15, 0, %0, c7, c1, 0	@ inv I-cache inner shareable)	\
+	UP(mcr	p15, 0, %0, c7, c5, 0	@ invalidate I-cache)		\
+	    :								\
 	    : "r" (0));
 #endif
 }
-- 
1.6.0.4

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Russell King - ARM Linux]

On Fri, Sep 03, 2010 at 05:27:25PM +0530, Shilimkar, Santosh wrote:
> Since UP/SMP both cases are handled, the above patch can be something
> like this now... 

No - this results in the instruction used for ARMv6 SMP systems being
changed to the ARMv7 instruction, which probably won't work.

[PATCH 2/6] ARM: Use SMP and UP macros for cacheflush

[Shilimkar, Santosh]

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Saturday, September 04, 2010 4:28 PM
> To: Shilimkar, Santosh
> Cc: Tony Lindgren; linux-omap at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Bryan Wu; Will Deacon
> Subject: Re: [PATCH 2/6] ARM: Use SMP and UP macros for cacheflush
> 
> On Fri, Sep 03, 2010 at 05:27:25PM +0530, Shilimkar, Santosh wrote:
> > Since UP/SMP both cases are handled, the above patch can be something
> > like this now...
> 
> No - this results in the instruction used for ARMv6 SMP systems being
> changed to the ARMv7 instruction, which probably won't work.
Ok. I get it now