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[54.240.197.231]) by smtp.gmail.com with ESMTPSA id e24-20020a5d5958000000b00317ab75748bsm1916735wri.49.2023.09.21.07.33.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Sep 2023 07:33:40 -0700 (PDT) From: Puranjay Mohan To: Xu Kuohai , ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, martin.lau@linux.dev, song@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, bpf@vger.kernel.org, kpsingh@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH bpf-next v5 1/3] arm64: patching: Add aarch64_insn_copy() In-Reply-To: <9084901f-730c-cf33-9337-f18a3c17283f@huaweicloud.com> References: <20230908144320.2474-1-puranjay12@gmail.com> <20230908144320.2474-2-puranjay12@gmail.com> <9084901f-730c-cf33-9337-f18a3c17283f@huaweicloud.com> Date: Thu, 21 Sep 2023 14:33:34 +0000 Message-ID: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_153343_770843_88052998 X-CRM114-Status: GOOD ( 22.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Xu Kuohai writes: > On 9/8/2023 10:43 PM, Puranjay Mohan wrote: >> This will be used by BPF JIT compiler to dump JITed binary to a RX huge >> page, and thus allow multiple BPF programs sharing the a huge (2MB) >> page. >> >> The bpf_prog_pack allocator that implements the above feature allocates >> a RX/RW buffer pair. The JITed code is written to the RW buffer and then >> this function will be used to copy the code from RW to RX buffer. >> >> Signed-off-by: Puranjay Mohan >> Acked-by: Song Liu >> --- >> arch/arm64/include/asm/patching.h | 1 + >> arch/arm64/kernel/patching.c | 41 +++++++++++++++++++++++++++++++ >> 2 files changed, 42 insertions(+) >> >> diff --git a/arch/arm64/include/asm/patching.h b/arch/arm64/include/asm/patching.h >> index 68908b82b168..f78a0409cbdb 100644 >> --- a/arch/arm64/include/asm/patching.h >> +++ b/arch/arm64/include/asm/patching.h >> @@ -8,6 +8,7 @@ int aarch64_insn_read(void *addr, u32 *insnp); >> int aarch64_insn_write(void *addr, u32 insn); >> >> int aarch64_insn_write_literal_u64(void *addr, u64 val); >> +void *aarch64_insn_copy(void *dst, const void *src, size_t len); >> >> int aarch64_insn_patch_text_nosync(void *addr, u32 insn); >> int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt); >> diff --git a/arch/arm64/kernel/patching.c b/arch/arm64/kernel/patching.c >> index b4835f6d594b..243d6ae8d2d8 100644 >> --- a/arch/arm64/kernel/patching.c >> +++ b/arch/arm64/kernel/patching.c >> @@ -105,6 +105,47 @@ noinstr int aarch64_insn_write_literal_u64(void *addr, u64 val) >> return ret; >> } >> >> +/** >> + * aarch64_insn_copy - Copy instructions into (an unused part of) RX memory >> + * @dst: address to modify >> + * @src: source of the copy >> + * @len: length to copy >> + * >> + * Useful for JITs to dump new code blocks into unused regions of RX memory. >> + */ >> +noinstr void *aarch64_insn_copy(void *dst, const void *src, size_t len) >> +{ >> + unsigned long flags; >> + size_t patched = 0; >> + size_t size; >> + void *waddr; >> + void *ptr; >> + int ret; >> + > > check whether the input address and length are aligned to instruction size? Will add a check that dst is aligned to instruction size and len is a multiple of instruction size. > >> + raw_spin_lock_irqsave(&patch_lock, flags); >> + >> + while (patched < len) { >> + ptr = dst + patched; >> + size = min_t(size_t, PAGE_SIZE - offset_in_page(ptr), >> + len - patched); >> + >> + waddr = patch_map(ptr, FIX_TEXT_POKE0); >> + ret = copy_to_kernel_nofault(waddr, src + patched, size); >> + patch_unmap(FIX_TEXT_POKE0); >> + >> + if (ret < 0) { >> + raw_spin_unlock_irqrestore(&patch_lock, flags); >> + return NULL; >> + } >> + patched += size; >> + } >> + raw_spin_unlock_irqrestore(&patch_lock, flags); >> + >> + caches_clean_inval_pou((uintptr_t)dst, (uintptr_t)dst + len); >> + > > seems flush_icache_range() or something like should be called here to > ensure the other CPUs' pipelines are cleared, otherwise the old instructions > at the dst address might be executed on other CPUs after the copy is complete, > which is not expected. Sure, I will use flush_icache_range() in place of caches_clean_inval_pou() in the next version > >> + return dst; >> +} >> + >> int __kprobes aarch64_insn_patch_text_nosync(void *addr, u32 insn) >> { >> u32 *tp = addr; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel