* [PATCH v5 1/3] arm64: ptrace: reload a syscall number after ptrace operations
From: Kees Cook @ 2014-07-23 15:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <53CF5E53.3060409@linaro.org>
On Wed, Jul 23, 2014 at 12:03 AM, AKASHI Takahiro
<takahiro.akashi@linaro.org> wrote:
> On 07/23/2014 05:15 AM, Kees Cook wrote:
>>
>> On Tue, Jul 22, 2014 at 2:14 AM, AKASHI Takahiro
>> <takahiro.akashi@linaro.org> wrote:
>>>
>>> Arm64 holds a syscall number in w8(x8) register. Ptrace tracer may change
>>> its value either to:
>>> * any valid syscall number to alter a system call, or
>>> * -1 to skip a system call
>>>
>>> This patch implements this behavior by reloading that value into
>>> syscallno
>>> in struct pt_regs after tracehook_report_syscall_entry() or
>>> secure_computing(). In case of '-1', a return value of system call can
>>> also
>>> be changed by the tracer setting the value to x0 register, and so
>>> sys_ni_nosyscall() should not be called.
>>>
>>> See also:
>>> 42309ab4, ARM: 8087/1: ptrace: reload syscall number after
>>> secure_computing() check
>>>
>>> Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
>>> ---
>>> arch/arm64/kernel/entry.S | 2 ++
>>> arch/arm64/kernel/ptrace.c | 13 +++++++++++++
>>> 2 files changed, 15 insertions(+)
>>>
>>> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
>>> index 5141e79..de8bdbc 100644
>>> --- a/arch/arm64/kernel/entry.S
>>> +++ b/arch/arm64/kernel/entry.S
>>> @@ -628,6 +628,8 @@ ENDPROC(el0_svc)
>>> __sys_trace:
>>> mov x0, sp
>>> bl syscall_trace_enter
>>> + cmp w0, #-1 // skip syscall?
>>> + b.eq ret_to_user
>>> adr lr, __sys_trace_return // return address
>>> uxtw scno, w0 // syscall number
>>> (possibly new)
>>> mov x1, sp // pointer to regs
>>> diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
>>> index 70526cf..100d7d1 100644
>>> --- a/arch/arm64/kernel/ptrace.c
>>> +++ b/arch/arm64/kernel/ptrace.c
>>> @@ -21,6 +21,7 @@
>>>
>>> #include <linux/audit.h>
>>> #include <linux/compat.h>
>>> +#include <linux/errno.h>
>>> #include <linux/kernel.h>
>>> #include <linux/sched.h>
>>> #include <linux/mm.h>
>>> @@ -1109,9 +1110,21 @@ static void tracehook_report_syscall(struct
>>> pt_regs *regs,
>>>
>>> asmlinkage int syscall_trace_enter(struct pt_regs *regs)
>>> {
>>> + unsigned long saved_x0, saved_x8;
>>> +
>>> + saved_x0 = regs->regs[0];
>>> + saved_x8 = regs->regs[8];
>>> +
>>> if (test_thread_flag(TIF_SYSCALL_TRACE))
>>> tracehook_report_syscall(regs, PTRACE_SYSCALL_ENTER);
>>>
>>> + regs->syscallno = regs->regs[8];
>>> + if ((long)regs->syscallno == ~0UL) { /* skip this syscall */
>>> + regs->regs[8] = saved_x8;
>>> + if (regs->regs[0] == saved_x0) /* not changed by user */
>>> + regs->regs[0] = -ENOSYS;
>>
>>
>> I'm not sure this is right compared to other architectures. Generally
>> when a tracer performs a syscall skip, it's up to them to also adjust
>> the return value. They may want to be faking a syscall, and what if
>> the value they want to return happens to be what x0 was going into the
>> tracer? It would have no way to avoid this -ENOSYS case. I think
>> things are fine without this test.
>
>
> Yeah, I know this issue, but was not sure that setting a return value
> is mandatory. (x86 seems to return -ENOSYS by default if not explicitly
> specified.)
> Is "fake a system call" a more appropriate word than "skip"?
I think this is just a matter of semantics and perspective. From the
kernel's perspective, it's always a "skip" since the syscall is never
actually executed. But from the perspective of userspace, it's really
up to the tracer to decide how it should be seen: the tracer could
return -ENOSYS, or a fake return value, etc. But generally, I think
"skip" is the most accurate term for this.
-Kees
--
Kees Cook
Chrome OS Security
^ permalink raw reply
* [PATCH 2/2] Adding lenovo in vendor
From: Andrew Lunn @ 2014-07-23 15:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140723134756.GG23220@titan.lakedaemon.net>
> > +lenovo LENOVO
>
> is this their official, registered company name?
http://www.lenovo.com/ww/lenovo/FAQs.html says
1. What is Lenovo?s stock symbol (ticker)?
HKSE: 992.hk
ADR (Level I): LNVGY
So i think lenovo is probably the more understandable vendor prefix,
even if it is not the official stock ticker.
However there official registered company name appears to be
Lenovo Group Limited.
Andrew
^ permalink raw reply
* omap-wakeupgen.c: Remove function for fix me
From: Nick Krause @ 2014-07-23 15:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140723074328.GI18374@atomide.com>
On Wed, Jul 23, 2014 at 3:43 AM, Tony Lindgren <tony@atomide.com> wrote:
> * Nick Krause <xerofoify@gmail.com> [140722 14:12]:
>> static void __init irq_pm_init(void)
>> 382 {
>> 383 /* FIXME: Remove this when MPU OSWR support is added */
>> 384 if (!soc_is_omap54xx())
>> 385 cpu_pm_register_notifier(&irq_notifier_block);
>> 386 }
>> I am wondering is this omap supported now if it is can I remove it?
>
> Does REVISIT cause issues for you with cscope? It may be easier to
> replace the cscope bugging FIXME statements with just REVISIT unless
> a real fix is provided.
>
> Regards,
>
> Tony
Very well then , seems like a good idea will try later.
Nick
^ permalink raw reply
* [PATCH] drivers: CCI: Correct use of ! and &
From: Will Deacon @ 2014-07-23 15:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9hhwqb42k63.fsf@arm.com>
On Wed, Jul 23, 2014 at 04:01:56PM +0100, Punit Agrawal wrote:
> > diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
> > index 5a86da9..7af78df 100644
> > --- a/drivers/bus/arm-cci.c
> > +++ b/drivers/bus/arm-cci.c
> > @@ -397,7 +397,8 @@ static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
> > hw_counter = &event->hw;
> >
> > /* Did this counter overflow? */
> > - if (!pmu_read_register(idx, CCI_PMU_OVRFLW) & CCI_PMU_OVRFLW_FLAG)
> > + if (!(pmu_read_register(idx, CCI_PMU_OVRFLW) &
> > + CCI_PMU_OVRFLW_FLAG))
> > continue;
>
>
> Going back to the manual, this fix looks correct.
>
> Acked-by: Punit Agrawal <punit.agrawal@arm.com>
>
> Will, would this go via your tree?
Given that you're happy with it, I don't mind which tree it goes in.
Probably deserves a CC stable on it too.
If you get stuck, put it in rmk's patch system.
Will
^ permalink raw reply
* [PATCH v2] cpufreq: tests: Providing cpufreq regression test
From: Andrew Lunn @ 2014-07-23 15:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKohpok++gPcNk9-E4MsFdNBy8qL7oLYvatk1EvcW1OHwroZXQ@mail.gmail.com>
On Wed, Jul 23, 2014 at 02:19:54PM +0530, Viresh Kumar wrote:
> On 23 July 2014 13:08, Lukasz Majewski <l.majewski@samsung.com> wrote:
> > Do you want to say that we have enough tests and we don't need more ?
>
> No. We don't have any tests at all :)
Not really true. I've found bugs triggering opps using cpufreq-bench.
http://marc.info/?l=linux-pm&m=138165517321579&w=2
and i hope you learned from that experience and run this tool when
making changes to the core.
There is an old writeup of cpufreq-bench here:
https://lwn.net/Articles/339862/
and the code itself is in the mainline tree, tools/power/cpupower/bench
Andrew
^ permalink raw reply
* [PATCH] drivers: CCI: Correct use of ! and &
From: Punit Agrawal @ 2014-07-23 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140707140538.GA4204@himangi-Dell>
Adding alkml and Will
Hi Himangi,
In future it would help if you send the patch to the the maintainers by
running the get_maintainers.pl script on the patch.
Himangi Saraogi <himangi774@gmail.com> writes:
> In commit ae91d60ba88ef0bdb1b5e9b2363bd52fc45d2af7, a bug was fixed that
> involved converting !x & y to !(x & y). The code below shows the same
> pattern, and thus should perhaps be fixed in the same way.
>
> The Coccinelle semantic patch that makes this change is as follows:
>
> // <smpl>
> @@ expression E1,E2; @@
> (
> !E1 & !E2
> |
> - !E1 & E2
> + !(E1 & E2)
> )
> // </smpl>
>
> Signed-off-by: Himangi Saraogi <himangi774@gmail.com>
> Acked-by: Julia Lawall <julia.lawall@lip6.fr>
> ---
> This is not tested and clearly changes the semantics, so it is only
> something to consider.
> drivers/bus/arm-cci.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
> index 5a86da9..7af78df 100644
> --- a/drivers/bus/arm-cci.c
> +++ b/drivers/bus/arm-cci.c
> @@ -397,7 +397,8 @@ static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
> hw_counter = &event->hw;
>
> /* Did this counter overflow? */
> - if (!pmu_read_register(idx, CCI_PMU_OVRFLW) & CCI_PMU_OVRFLW_FLAG)
> + if (!(pmu_read_register(idx, CCI_PMU_OVRFLW) &
> + CCI_PMU_OVRFLW_FLAG))
> continue;
Going back to the manual, this fix looks correct.
Acked-by: Punit Agrawal <punit.agrawal@arm.com>
Will, would this go via your tree?
>
> pmu_write_register(CCI_PMU_OVRFLW_FLAG, idx, CCI_PMU_OVRFLW);
^ permalink raw reply
* [PATCH 3/3] pinctrl: rockchip: add drive-strength control for rk3288
From: Linus Walleij @ 2014-07-23 14:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <29291825.rqOIHNJZsg@diego>
On Sun, Jul 20, 2014 at 1:50 AM, Heiko St?bner <heiko@sntech.de> wrote:
> The rk3288 is the first Rockchip soc handling the drive strength on a per-pin
> basis, while the older ones can set the drive-strength only for specific
> pin-groups. Therefore limit setting the drive-strength to this soc for now.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Patch applied.
Others SoC:s have opted to create sub-drivers on a per-soc basis
when stuff gets too complicated, please keep this in mind if the
file starts growing wild...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v3 3/3] MAINTAINERS: Add dwc3-st.c file to ARCH/STI architecture
From: Peter Griffin @ 2014-07-23 14:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406126915-30601-1-git-send-email-peter.griffin@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 702ca10..269ad3b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1325,6 +1325,7 @@ F: drivers/pinctrl/pinctrl-st.c
F: drivers/media/rc/st_rc.c
F: drivers/i2c/busses/i2c-st.c
F: drivers/tty/serial/st-asc.c
+F: drivers/usb/dwc3/dwc3-st.c
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
--
1.9.1
^ permalink raw reply related
* [PATCH v3 2/3] usb: dwc3: dwc3-st: Add st-dwc3 devicetree bindings documentation
From: Peter Griffin @ 2014-07-23 14:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406126915-30601-1-git-send-email-peter.griffin@linaro.org>
This patch documents the device tree documentation required for
the ST usb3 controller glue layer found in STiH407 devices.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
Documentation/devicetree/bindings/usb/dwc3-st.txt | 69 +++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/dwc3-st.txt
diff --git a/Documentation/devicetree/bindings/usb/dwc3-st.txt b/Documentation/devicetree/bindings/usb/dwc3-st.txt
new file mode 100644
index 0000000..de3fea3
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/dwc3-st.txt
@@ -0,0 +1,69 @@
+ST DWC3 glue logic
+
+This file documents the parameters for the dwc3-st driver.
+This driver controls the glue logic used to configure the dwc3 core on
+STiH407 based platforms.
+
+Required properties:
+ - compatible : must be "st,stih407-dwc3"
+ - reg : glue logic base address and USB syscfg ctrl register offset
+ - reg-names : should be "reg-glue" and "syscfg-reg"
+ - st,syscon : should be phandle to system configuration node which
+ encompasses the glue registers
+ - resets : list of phandle and reset specifier pairs. There should be two entries, one
+ for the powerdown and softreset lines of the usb3 IP
+ - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
+See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
+See: Documentation/devicetree/bindings/reset/reset.txt
+
+ - #address-cells, #size-cells : should be '1' if the device has sub-nodes
+ with 'reg' property
+
+ - pinctl-names : A pinctrl state named "default" must be defined
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+ - pinctrl-0 : Pin control group
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+ - ranges : allows valid 1:1 translation between child's address space and
+ parent's address space
+
+Sub-nodes:
+The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
+example below. The DT binding details of dwc3 can be found in:
+Documentation/devicetree/bindings/usb/dwc3.txt
+
+NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value
+is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
+or "device".
+
+[1] Documentation/devicetree/bindings/usb/generic.txt
+
+Example:
+
+st_dwc3: dwc3 at 8f94000 {
+ status = "disabled";
+ compatible = "st,stih407-dwc3";
+ reg = <0x08f94000 0x1000>, <0x110 0x4>;
+ reg-names = "reg-glue", "syscfg-reg";
+ st,syscfg = <&syscfg_core>;
+ resets = <&powerdown STIH407_USB3_POWERDOWN>;
+ <&softreset STIH407_MIPHY2_SOFTRESET>;
+ reset-names = "powerdown",
+ "softreset";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+ ranges;
+
+ dwc3: dwc3 at 9900000 {
+ compatible = "snps,dwc3";
+ reg = <0x09900000 0x100000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
+ dr_mode = "host"
+ usb-phy = <&usb3_phy>;
+ phy-names = "usb2-phy";
+ phys = <&usb2_picophy2>;
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH v3 1/3] usb: dwc3: add ST dwc3 glue layer to manage dwc3 HC
From: Peter Griffin @ 2014-07-23 14:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406126915-30601-1-git-send-email-peter.griffin@linaro.org>
This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It manages the powerdown signal,
and configures the internal glue logic and syscfg registers.
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
drivers/usb/dwc3/Kconfig | 9 ++
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-st.c | 338 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 348 insertions(+)
create mode 100644 drivers/usb/dwc3/dwc3-st.c
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 8eb996e..6c85c43 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -79,6 +79,15 @@ config USB_DWC3_KEYSTONE
Support of USB2/3 functionality in TI Keystone2 platforms.
Say 'Y' or 'M' here if you have one such device
+config USB_DWC3_ST
+ tristate "STMicroelectronics Platforms"
+ depends on ARCH_STI && OF
+ default USB_DWC3_HOST
+ help
+ STMicroelectronics SoCs with one DesignWare Core USB3 IP
+ inside (i.e. STiH407).
+ Say 'Y' or 'M' if you have one such device.
+
comment "Debugging features"
config USB_DWC3_DEBUG
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 10ac3e7..11c9f54 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o
obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o
+obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o
diff --git a/drivers/usb/dwc3/dwc3-st.c b/drivers/usb/dwc3/dwc3-st.c
new file mode 100644
index 0000000..a93ea19
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-st.c
@@ -0,0 +1,338 @@
+/**
+ * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms
+ *
+ * This is a small driver for the dwc3 to provide the glue logic
+ * to configure the controller. Tested on STi platforms.
+ *
+ * Copyright (C) 2014 Stmicroelectronics
+ *
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Contributors: Aymen Bouattay <aymen.bouattay@st.com>
+ * Peter Griffin <peter.griffin@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Inspired by dwc3-omap.c and dwc3-exynos.c.
+ */
+
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/usb/of.h>
+
+#include "core.h"
+#include "io.h"
+
+/* glue registers */
+#define CLKRST_CTRL 0x00
+#define AUX_CLK_EN BIT(0)
+#define SW_PIPEW_RESET_N BIT(4)
+#define EXT_CFG_RESET_N BIT(8)
+/*
+ * 1'b0 : The host controller complies with the xHCI revision 0.96
+ * 1'b1 : The host controller complies with the xHCI revision 1.0
+ */
+#define XHCI_REVISION BIT(12)
+
+#define USB2_VBUS_MNGMNT_SEL1 0x2C
+/*
+ * For all fields in USB2_VBUS_MNGMNT_SEL1
+ * 2?b00 : Override value from Reg 0x30 is selected
+ * 2?b01 : utmiotg_<signal_name> from usb3_top is selected
+ * 2?b10 : pipew_<signal_name> from PIPEW instance is selected
+ * 2?b11 : value is 1'b0
+ */
+#define REG30 0x0
+#define UTMIOTG 0x1
+#define PIPEW 0x2
+#define ZERO 0x3
+
+#define SEL_OVERRIDE_VBUSVALID(n) (n << 0)
+#define SEL_OVERRIDE_POWERPRESENT(n) (n << 4)
+#define SEL_OVERRIDE_BVALID(n) (n << 8)
+
+/* Static DRD configuration */
+#define USB_HOST_DEFAULT_MASK 0xffe
+#define USB_SET_PORT_DEVICE 0x1
+
+/**
+ * struct st_dwc3 - st-dwc3 driver private structure
+ * @dwc3: platform device pointer
+ * @dev: device pointer
+ * @glue_base ioaddr for the glue registers
+ * @regmap regmap pointer for getting syscfg
+ * @syscfg_reg_off usb syscfg control offset
+ * @dr_mode drd static host/device config
+ * @rstc_pwrdn rest controller for powerdown signal
+ * @rstc_rst reset controller for softreset signal
+ *
+ */
+
+struct st_dwc3 {
+ struct device *dev;
+ void __iomem *glue_base;
+ struct regmap *regmap;
+ int syscfg_reg_off;
+ enum usb_dr_mode dr_mode;
+ struct reset_control *rstc_pwrdn;
+ struct reset_control *rstc_rst;
+};
+
+static inline u32 st_dwc3_readl(void __iomem *base, u32 offset)
+{
+ return readl_relaxed(base + offset);
+}
+
+static inline void st_dwc3_writel(void __iomem *base, u32 offset, u32 value)
+{
+ writel_relaxed(value, base + offset);
+}
+
+/**
+ * st_dwc3_drd_init: program the port
+ * @dwc3_data: driver private structure
+ * Description: this function is to program the port as either host or device
+ * according to the static configuration passed from devicetree.
+ * OTG and dual role are not yet supported!
+ */
+static int st_dwc3_drd_init(struct st_dwc3 *dwc3_data)
+{
+ u32 val;
+ int err;
+
+ err = regmap_read(dwc3_data->regmap, dwc3_data->syscfg_reg_off, &val);
+ if (err)
+ return err;
+
+ switch (dwc3_data->dr_mode) {
+ case USB_DR_MODE_PERIPHERAL:
+ val |= USB_SET_PORT_DEVICE;
+ dev_dbg(dwc3_data->dev, "Configuring as Device\n");
+ break;
+
+ case USB_DR_MODE_HOST:
+ val &= USB_HOST_DEFAULT_MASK;
+ dev_dbg(dwc3_data->dev, "Configuring as Host\n");
+ break;
+
+ default:
+ dev_err(dwc3_data->dev, "Unsupported mode of operation %d\n"
+ , dwc3_data->dr_mode);
+ return -EINVAL;
+ }
+
+ return regmap_write(dwc3_data->regmap, dwc3_data->syscfg_reg_off, val);
+}
+
+/**
+ * st_dwc3_init: init the controller via glue logic
+ * @dwc3_data: driver private structure
+ */
+static void st_dwc3_init(struct st_dwc3 *dwc3_data)
+{
+
+ u32 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL);
+
+ reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION;
+ reg &= ~SW_PIPEW_RESET_N;
+ st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg);
+
+ /* configure mux for vbus, powerpresent and bvalid signals */
+ reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1);
+
+ reg |= SEL_OVERRIDE_VBUSVALID(UTMIOTG) |
+ SEL_OVERRIDE_POWERPRESENT(UTMIOTG) |
+ SEL_OVERRIDE_BVALID(UTMIOTG);
+
+ st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg);
+
+ reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL);
+ reg |= SW_PIPEW_RESET_N;
+ st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg);
+}
+
+static int st_dwc3_probe(struct platform_device *pdev)
+{
+ struct st_dwc3 *dwc3_data;
+ struct resource *res;
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node, *child;
+ struct regmap *regmap;
+ int ret;
+
+ dwc3_data = devm_kzalloc(dev, sizeof(*dwc3_data), GFP_KERNEL);
+ if (!dwc3_data)
+ return -ENOMEM;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg-glue");
+ dwc3_data->glue_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(dwc3_data->glue_base))
+ return PTR_ERR(dwc3_data->glue_base);
+
+ regmap = syscon_regmap_lookup_by_phandle(node, "st,syscfg");
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ dma_set_coherent_mask(dev, dev->coherent_dma_mask);
+ dwc3_data->dev = dev;
+ dwc3_data->regmap = regmap;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "syscfg-reg");
+ if (!res) {
+ ret = -ENXIO;
+ goto undo_platform_dev_alloc;
+ }
+
+ dwc3_data->syscfg_reg_off = res->start;
+
+ dev_dbg(&pdev->dev, "glue-logic addr 0x%p, syscfg-reg offset 0x%x\n",
+ dwc3_data->glue_base, dwc3_data->syscfg_reg_off);
+
+ dwc3_data->rstc_pwrdn = devm_reset_control_get(dev, "powerdown");
+ if (IS_ERR(dwc3_data->rstc_pwrdn)) {
+ dev_err(&pdev->dev, "could not get power controller\n");
+ ret = PTR_ERR(dwc3_data->rstc_pwrdn);
+ goto undo_platform_dev_alloc;
+ }
+
+ /* Manage PowerDown */
+ reset_control_deassert(dwc3_data->rstc_pwrdn);
+
+ dwc3_data->rstc_rst = devm_reset_control_get(dev, "softreset");
+ if (IS_ERR(dwc3_data->rstc_rst)) {
+ dev_err(&pdev->dev, "could not get reset controller\n");
+ ret = PTR_ERR(dwc3_data->rstc_pwrdn);
+ goto undo_powerdown;
+ }
+
+ /* Manage SoftReset */
+ reset_control_deassert(dwc3_data->rstc_rst);
+
+ child = of_get_child_by_name(node, "dwc3");
+ if (!child) {
+ dev_err(&pdev->dev, "failed to find dwc3 core node\n");
+ ret = -ENODEV;
+ goto undo_softreset;
+ }
+
+ dwc3_data->dr_mode = of_usb_get_dr_mode(child);
+
+ /* Allocate and initialize the core */
+ ret = of_platform_populate(node, NULL, NULL, dev);
+ if (ret) {
+ dev_err(dev, "failed to add dwc3 core\n");
+ goto undo_softreset;
+ }
+
+ /*
+ * Configure the USB port as device or host according to the static
+ * configuration passed from DT.
+ * DRD is the only mode currently supported so this will be enhanced
+ * as soon as OTG is available.
+ */
+ ret = st_dwc3_drd_init(dwc3_data);
+ if (ret) {
+ dev_err(dev, "drd initialisation failed\n");
+ goto undo_softreset;
+ }
+
+ /* ST glue logic init */
+ st_dwc3_init(dwc3_data);
+
+ platform_set_drvdata(pdev, dwc3_data);
+ return 0;
+
+undo_softreset:
+ reset_control_assert(dwc3_data->rstc_rst);
+undo_powerdown:
+ reset_control_assert(dwc3_data->rstc_pwrdn);
+undo_platform_dev_alloc:
+ platform_device_put(pdev);
+ return ret;
+}
+
+
+static int st_dwc3_remove_child(struct device *dev, void *c)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+
+ of_device_unregister(pdev);
+
+ return 0;
+}
+
+static int st_dwc3_remove(struct platform_device *pdev)
+{
+ struct st_dwc3 *dwc3_data = platform_get_drvdata(pdev);
+
+ device_for_each_child(&pdev->dev, NULL, st_dwc3_remove_child);
+
+ reset_control_assert(dwc3_data->rstc_pwrdn);
+ reset_control_assert(dwc3_data->rstc_rst);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int st_dwc3_suspend(struct device *dev)
+{
+ struct st_dwc3 *dwc3_data = dev_get_drvdata(dev);
+
+ reset_control_assert(dwc3_data->rstc_pwrdn);
+ reset_control_assert(dwc3_data->rstc_rst);
+
+ pinctrl_pm_select_sleep_state(dev);
+
+ return 0;
+}
+
+static int st_dwc3_resume(struct device *dev)
+{
+ struct st_dwc3 *dwc3_data = dev_get_drvdata(dev);
+
+ pinctrl_pm_select_default_state(dev);
+
+ reset_control_deassert(dwc3_data->rstc_pwrdn);
+ reset_control_deassert(dwc3_data->rstc_rst);
+
+ return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static SIMPLE_DEV_PM_OPS(st_dwc3_dev_pm_ops, st_dwc3_suspend, st_dwc3_resume);
+
+static const struct of_device_id st_dwc3_match[] = {
+ { .compatible = "st,stih407-dwc3" },
+ { /* sentinel */ },
+};
+
+MODULE_DEVICE_TABLE(of, st_dwc3_match);
+
+static struct platform_driver st_dwc3_driver = {
+ .probe = st_dwc3_probe,
+ .remove = st_dwc3_remove,
+ .driver = {
+ .name = "usb-st-dwc3",
+ .of_match_table = st_dwc3_match,
+ .pm = &st_dwc3_dev_pm_ops,
+ },
+};
+
+module_platform_driver(st_dwc3_driver);
+
+MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
+MODULE_DESCRIPTION("DesignWare USB3 STi Glue Layer");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related
* [PATCH v3 0/3] Add ST dwc3 glue layer driver
From: Peter Griffin @ 2014-07-23 14:48 UTC (permalink / raw)
To: linux-arm-kernel
This series adds support for the ST glue logic which wraps the DWC3 controller
on STiH407 SoC family chipsets.
Changes since v2
- Use dr_mode for host/device static configuration
- Manage shared reset signal to usbss to avoid hang if probing before usb3 phy
- Remove DT checks and make driver depend on OF
- Change some #define to use BIT macro
- Make some comments clearer
- Use kerneldoc for struct documentation
- Remove udelay
- Let DT create platform_devices, and remove legacy alloc
- Change some logging levels to dev_dbg
- Various whitespace and formatting cleanup
- Use SIMPLE_DEV_PM_OPS()
- Add const to of_device struct
- Reorder header files alphabetically
- Use devm_ioremap_resource instead of devm_request_and_ioremap
- Remove of_match_ptr()
Peter Griffin (3):
usb: dwc3: add ST dwc3 glue layer to manage dwc3 HC
usb: dwc3: dwc3-st: Add st-dwc3 devicetree bindings documentation
MAINTAINERS: Add dwc3-st.c file to ARCH/STI architecture
Documentation/devicetree/bindings/usb/dwc3-st.txt | 69 +++++
MAINTAINERS | 1 +
drivers/usb/dwc3/Kconfig | 9 +
drivers/usb/dwc3/Makefile | 1 +
drivers/usb/dwc3/dwc3-st.c | 337 ++++++++++++++++++++++
5 files changed, 417 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/dwc3-st.txt
create mode 100644 drivers/usb/dwc3/dwc3-st.c
--
1.9.1
^ permalink raw reply
* [PATCH 2/3] pinctrl: rockchip: add separate type for rk3288
From: Linus Walleij @ 2014-07-23 14:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <12335737.BWge8alrAi@diego>
On Sun, Jul 20, 2014 at 1:49 AM, Heiko St?bner <heiko@sntech.de> wrote:
> An upcoming pinctrl function of the rk3288 differs again from everything else,
> so we'll need a separate type for it.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Patch applied. I have one of those on my desk now...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2 6/6] ARM: sunxi: Add A31 RTC driver to multi_v7_defconfig
From: Chen-Yu Tsai @ 2014-07-23 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406126338-15062-1-git-send-email-wens@csie.org>
Now that we have a driver for A31's RTC, enable it
in multi_v7_defconfig.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index a62ca27..130dd8d 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -346,6 +346,7 @@ CONFIG_RTC_DRV_TPS65910=y
CONFIG_RTC_DRV_EM3027=y
CONFIG_RTC_DRV_PL031=y
CONFIG_RTC_DRV_VT8500=y
+CONFIG_RTC_DRV_SUN6I=y
CONFIG_RTC_DRV_SUNXI=y
CONFIG_RTC_DRV_MV=y
CONFIG_RTC_DRV_TEGRA=y
--
2.0.1
^ permalink raw reply related
* [PATCH v2 5/6] ARM: sunxi: Add A31 RTC driver to sunxi_defconfig
From: Chen-Yu Tsai @ 2014-07-23 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406126338-15062-1-git-send-email-wens@csie.org>
Now that we have a driver for A31's RTC, enable it
in the default sunxi config.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index 7209bfd..0abc2ab 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -93,6 +93,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_INTF_SYSFS is not set
# CONFIG_RTC_INTF_PROC is not set
+CONFIG_RTC_DRV_SUN6I=y
CONFIG_RTC_DRV_SUNXI=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_PHY_SUN4I_USB=y
--
2.0.1
^ permalink raw reply related
* [PATCH v2 4/6] ARM: dts: sun8i: add rtc device node
From: Chen-Yu Tsai @ 2014-07-23 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406126338-15062-1-git-send-email-wens@csie.org>
sun8i shares the same rtc hardware as sun6i. Now that we have a driver
for it, add a device node to the DTSI for it so we can use it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun8i-a23.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index 54ac0787..e0d1048 100644
--- a/arch/arm/boot/dts/sun8i-a23.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -285,6 +285,12 @@
interrupts = <1 9 0xf04>;
};
+ rtc: rtc at 01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <0 40 4>;
+ };
+
prcm at 01f01400 {
compatible = "allwinner,sun8i-a23-prcm";
reg = <0x01f01400 0x200>;
--
2.0.1
^ permalink raw reply related
* [PATCH v2 3/6] ARM: dts: sun6i: add rtc device node
From: Chen-Yu Tsai @ 2014-07-23 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406126338-15062-1-git-send-email-wens@csie.org>
Now that we have a driver for sun6i's rtc hardware, add a device node
for it so we can use it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 44b07e5..6a16019 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -779,6 +779,12 @@
interrupts = <1 9 0xf04>;
};
+ rtc: rtc at 01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <0 40 4>;
+ };
+
nmi_intc: interrupt-controller at 01f00c0c {
compatible = "allwinner,sun6i-a31-sc-nmi";
interrupt-controller;
--
2.0.1
^ permalink raw reply related
* [PATCH v2 2/6] rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc
From: Chen-Yu Tsai @ 2014-07-23 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406126338-15062-1-git-send-email-wens@csie.org>
Now that we have Kconfig options for individual sunxi platforms, let
the rtc-sunxi driver depend on the platforms that actually have this
hardware, sun4i and sun7i.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/rtc/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index dde2b57..f933b4b 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1176,7 +1176,7 @@ config RTC_DRV_SUN6I
config RTC_DRV_SUNXI
tristate "Allwinner sun4i/sun7i RTC"
- depends on ARCH_SUNXI
+ depends on MACH_SUN4I || MACH_SUN7I
help
If you say Y here you will get support for the RTC found on
Allwinner A10/A20.
--
2.0.1
^ permalink raw reply related
* [PATCH v2 1/6] rtc: sun6i: Add sun6i RTC driver
From: Chen-Yu Tsai @ 2014-07-23 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1406126338-15062-1-git-send-email-wens@csie.org>
This patch introduces the driver for the RTC in the Allwinner A31 and
A23 SoCs.
Unlike the RTC found in A10/A20 SoCs, which was part of the timer, the
RTC in A31/A23 are a separate hardware block, which also contain a few
controls for the RTC block hardware (a regulator and RTC block GPIO pin
latches), while also having separate interrupts for the alarms.
The hardware is different enough to make a different driver for it.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
.../devicetree/bindings/rtc/sun6i-rtc.txt | 17 +
drivers/rtc/Kconfig | 7 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-sun6i.c | 448 +++++++++++++++++++++
4 files changed, 473 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
create mode 100644 drivers/rtc/rtc-sun6i.c
diff --git a/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
new file mode 100644
index 0000000..b18927c
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
@@ -0,0 +1,17 @@
+* sun6i Real Time Clock
+
+RTC controller for the Allwinner A31
+
+Required properties:
+- compatible : Should be "allwinner,sun6i-a31-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: IRQ line for the RTC alarm 0.
+
+Example:
+
+rtc: rtc at 01f00000 {
+ compatible = "allwinner,sun6i-a31-rtc";
+ reg = <0x01f00000 0x54>;
+ interrupts = <0 40 4>;
+};
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 0754f5c..dde2b57 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1167,6 +1167,13 @@ config RTC_DRV_SUN4V
If you say Y here you will get support for the Hypervisor
based RTC on SUN4V systems.
+config RTC_DRV_SUN6I
+ tristate "Allwinner A31 RTC"
+ depends on MACH_SUN6I || MACH_SUN8I
+ help
+ If you say Y here you will get support for the RTC found on
+ Allwinner A31.
+
config RTC_DRV_SUNXI
tristate "Allwinner sun4i/sun7i RTC"
depends on ARCH_SUNXI
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 70347d0..a47df29 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -123,6 +123,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o
obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o
obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o
obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o
+obj-$(CONFIG_RTC_DRV_SUN6I) += rtc-sun6i.o
obj-$(CONFIG_RTC_DRV_SUNXI) += rtc-sunxi.o
obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o
obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o
diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
new file mode 100644
index 0000000..069e8f9
--- /dev/null
+++ b/drivers/rtc/rtc-sun6i.c
@@ -0,0 +1,448 @@
+/*
+ * An RTC driver for Allwinner A31/A23
+ *
+ * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
+ *
+ * based on rtc-sunxi.c
+ *
+ * An RTC driver for Allwinner A10/A20
+ *
+ * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+#include <linux/types.h>
+
+/* Control register */
+#define SUN6I_LOSC_CTRL 0x0000
+#define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
+#define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
+#define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
+#define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
+
+/* RTC */
+#define SUN6I_RTC_YMD 0x0010
+#define SUN6I_RTC_HMS 0x0014
+
+/* Alarm 0 (counter) */
+#define SUN6I_ALRM_COUNTER 0x0020
+#define SUN6I_ALRM_CUR_VAL 0x0024
+#define SUN6I_ALRM_EN 0x0028
+#define SUN6I_ALRM_EN_CNT_EN BIT(0)
+#define SUN6I_ALRM_IRQ_EN 0x002c
+#define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
+#define SUN6I_ALRM_IRQ_STA 0x0030
+#define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
+
+/* Alarm 1 (wall clock) */
+#define SUN6I_ALRM1_EN 0x0044
+#define SUN6I_ALRM1_IRQ_EN 0x0048
+#define SUN6I_ALRM1_IRQ_STA 0x004c
+#define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
+
+/* Alarm config */
+#define SUN6I_ALARM_CONFIG 0x0050
+#define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
+
+/*
+ * Get date values
+ */
+#define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
+#define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
+#define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
+#define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
+
+/*
+ * Get time values
+ */
+#define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
+#define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
+#define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
+
+/*
+ * Set date values
+ */
+#define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
+#define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
+#define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
+#define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
+
+/*
+ * Set time values
+ */
+#define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
+#define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
+#define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
+
+/*
+ * The year parameter passed to the driver is usually an offset relative to
+ * the year 1900. This macro is used to convert this offset to another one
+ * relative to the minimum year allowed by the hardware.
+ *
+ * The year range is 1970 - 2033. This range is selected to match Allwinner's
+ * driver, even though it is somewhat limited.
+ */
+#define SUN6I_YEAR_MIN 1970
+#define SUN6I_YEAR_MAX 2033
+#define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
+
+struct sun6i_rtc_dev {
+ struct rtc_device *rtc;
+ struct device *dev;
+ void __iomem *base;
+ int irq;
+ unsigned long alarm;
+};
+
+static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
+{
+ struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
+ u32 val;
+
+ val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
+
+ if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
+ val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
+ writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
+
+ rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
+
+ return IRQ_HANDLED;
+ }
+
+ return IRQ_NONE;
+}
+
+static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
+{
+ u32 alrm_val = 0;
+ u32 alrm_irq_val = 0;
+ u32 alrm_wake_val = 0;
+
+ if (to) {
+ alrm_val = SUN6I_ALRM_EN_CNT_EN;
+ alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
+ alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
+ } else {
+ writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
+ chip->base + SUN6I_ALRM_IRQ_STA);
+ }
+
+ writel(alrm_val, chip->base + SUN6I_ALRM_EN);
+ writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
+ writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
+}
+
+static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
+{
+ struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+ u32 date, time;
+
+ /*
+ * read again in case it changes
+ */
+ do {
+ date = readl(chip->base + SUN6I_RTC_YMD);
+ time = readl(chip->base + SUN6I_RTC_HMS);
+ } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
+ (time != readl(chip->base + SUN6I_RTC_HMS)));
+
+ rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
+ rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
+ rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
+
+ rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
+ rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
+ rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
+
+ rtc_tm->tm_mon -= 1;
+
+ /*
+ * switch from (data_year->min)-relative offset to
+ * a (1900)-relative one
+ */
+ rtc_tm->tm_year += SUN6I_YEAR_OFF;
+
+ return rtc_valid_tm(rtc_tm);
+}
+
+static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{
+ struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+ u32 alrm_st;
+ u32 alrm_en;
+
+ alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
+ alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
+ wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
+ wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
+ rtc_time_to_tm(chip->alarm, &wkalrm->time);
+
+ return 0;
+}
+
+static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
+{
+ struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+ struct rtc_time *alrm_tm = &wkalrm->time;
+ struct rtc_time tm_now;
+ unsigned long time_now = 0;
+ unsigned long time_set = 0;
+ unsigned long time_gap = 0;
+ int ret = 0;
+
+ ret = sun6i_rtc_gettime(dev, &tm_now);
+ if (ret < 0) {
+ dev_err(dev, "Error in getting time\n");
+ return -EINVAL;
+ }
+
+ rtc_tm_to_time(alrm_tm, &time_set);
+ rtc_tm_to_time(&tm_now, &time_now);
+ if (time_set <= time_now) {
+ dev_err(dev, "Date to set in the past\n");
+ return -EINVAL;
+ }
+
+ time_gap = time_set - time_now;
+
+ if (time_gap > U32_MAX) {
+ dev_err(dev, "Date too far in the future\n");
+ return -EINVAL;
+ }
+
+ sun6i_rtc_setaie(0, chip);
+ writel(0, chip->base + SUN6I_ALRM_COUNTER);
+ usleep_range(100, 300);
+
+ writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
+ chip->alarm = time_set;
+
+ sun6i_rtc_setaie(wkalrm->enabled, chip);
+
+ return 0;
+}
+
+static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
+ unsigned int mask, unsigned int ms_timeout)
+{
+ const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
+ u32 reg;
+
+ do {
+ reg = readl(chip->base + offset);
+ reg &= mask;
+
+ if (!reg)
+ return 0;
+
+ } while (time_before(jiffies, timeout));
+
+ return -ETIMEDOUT;
+}
+
+static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
+{
+ struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+ u32 date = 0;
+ u32 time = 0;
+ int year;
+
+ year = rtc_tm->tm_year + 1900;
+ if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
+ dev_err(dev, "rtc only supports year in range %d - %d\n",
+ SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
+ return -EINVAL;
+ }
+
+ rtc_tm->tm_year -= SUN6I_YEAR_OFF;
+ rtc_tm->tm_mon += 1;
+
+ date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
+ SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
+ SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
+
+ if (is_leap_year(year))
+ date |= SUN6I_LEAP_SET_VALUE(1);
+
+ time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
+ SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
+ SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
+
+ /* Check whether registers are writable */
+ if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
+ SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
+ dev_err(dev, "rtc is still busy.\n");
+ return -EBUSY;
+ }
+
+ writel(time, chip->base + SUN6I_RTC_HMS);
+
+ /*
+ * After writing the RTC HH-MM-SS register, the
+ * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
+ * be cleared until the real writing operation is finished
+ */
+
+ if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
+ SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
+ dev_err(dev, "Failed to set rtc time.\n");
+ return -ETIMEDOUT;
+ }
+
+ writel(date, chip->base + SUN6I_RTC_YMD);
+
+ /*
+ * After writing the RTC YY-MM-DD register, the
+ * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
+ * be cleared until the real writing operation is finished
+ */
+
+ if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
+ SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
+ dev_err(dev, "Failed to set rtc time.\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+{
+ struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+
+ if (!enabled)
+ sun6i_rtc_setaie(enabled, chip);
+
+ return 0;
+}
+
+static const struct rtc_class_ops sun6i_rtc_ops = {
+ .read_time = sun6i_rtc_gettime,
+ .set_time = sun6i_rtc_settime,
+ .read_alarm = sun6i_rtc_getalarm,
+ .set_alarm = sun6i_rtc_setalarm,
+ .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
+};
+
+static int sun6i_rtc_probe(struct platform_device *pdev)
+{
+ struct sun6i_rtc_dev *chip;
+ struct resource *res;
+ int ret;
+
+ chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, chip);
+ chip->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ chip->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(chip->base))
+ return PTR_ERR(chip->base);
+
+ chip->irq = platform_get_irq(pdev, 0);
+ if (chip->irq < 0) {
+ dev_err(&pdev->dev, "No IRQ resource\n");
+ return chip->irq;
+ }
+
+ ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
+ 0, dev_name(&pdev->dev), chip);
+ if (ret) {
+ dev_err(&pdev->dev, "Could not request IRQ\n");
+ return ret;
+ }
+
+ /* clear the alarm counter value */
+ writel(0, chip->base + SUN6I_ALRM_COUNTER);
+
+ /* disable counter alarm */
+ writel(0, chip->base + SUN6I_ALRM_EN);
+
+ /* disable counter alarm interrupt */
+ writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
+
+ /* disable week alarm */
+ writel(0, chip->base + SUN6I_ALRM1_EN);
+
+ /* disable week alarm interrupt */
+ writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
+
+ /* clear counter alarm pending interrupts */
+ writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
+ SUN6I_ALRM_IRQ_STA);
+
+ /* clear week alarm pending interrupts */
+ writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, chip->base +
+ SUN6I_ALRM1_IRQ_STA);
+
+ /* disable alarm wakeup */
+ writel(0, chip->base + SUN6I_ALARM_CONFIG);
+
+ chip->rtc = rtc_device_register("rtc-sun6i", &pdev->dev,
+ &sun6i_rtc_ops, THIS_MODULE);
+ if (IS_ERR(chip->rtc)) {
+ dev_err(&pdev->dev, "unable to register device\n");
+ return PTR_ERR(chip->rtc);
+ }
+
+ dev_info(&pdev->dev, "RTC enabled\n");
+
+ return 0;
+}
+
+static int sun6i_rtc_remove(struct platform_device *pdev)
+{
+ struct sun6i_rtc_dev *chip = platform_get_drvdata(pdev);
+
+ rtc_device_unregister(chip->rtc);
+
+ return 0;
+}
+
+static const struct of_device_id sun6i_rtc_dt_ids[] = {
+ { .compatible = "allwinner,sun6i-a31-rtc" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
+
+static struct platform_driver sun6i_rtc_driver = {
+ .probe = sun6i_rtc_probe,
+ .remove = sun6i_rtc_remove,
+ .driver = {
+ .name = "sun6i-rtc",
+ .owner = THIS_MODULE,
+ .of_match_table = sun6i_rtc_dt_ids,
+ },
+};
+
+module_platform_driver(sun6i_rtc_driver);
+
+MODULE_DESCRIPTION("sun6i RTC driver");
+MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
+MODULE_LICENSE("GPL");
--
2.0.1
^ permalink raw reply related
* [PATCH v2 0/6] ARM: sunxi: RTC support for A31/A23
From: Chen-Yu Tsai @ 2014-07-23 14:38 UTC (permalink / raw)
To: linux-arm-kernel
Hi everyone,
This is v2 of the sun6i RTC series. This series adds support for
the RTC in A31 and A23 SoCs. The series applies to sunxi-next.
The A31 has a new RTC block that is separate from the timer block.
It has separate interrupts for each of the alarms, and a different
format for the counter alarm. The driver has been tested on the
A31 Hummingbird, and the A23 tablet I'm using to work on sun8i
support.
Patch 1 adds the driver for the RTC.
Patch 2 is a minor cleanup. This makes rtc-sunxi depend on sun4i or
sun7i, the 2 platforms the driver is actually used on.
Patch 3 adds the RTC device node to the sun6i DTSI.
Patch 4 adds the RTC device node to the sun8i DTSI.
Patch 5 adds enables rtc-sun6i in the sunxi defconfig.
Patch 6 adds enables rtc-sun6i in the multi_v7 defconfig.
This patch applies to arm-soc/next/defconfig (e9a86d96)
Changes since v1:
- Enable rtc-sun6i in multi_v7_defconfig
- Cleanup the time/date GET/SET macros
- Use GENMASK for control register mask
- Change Kconfig option to show 'A31'
- Remove leftover comment from rtc-sun4i
- Remove extra newline
Cheers
ChenYu
Chen-Yu Tsai (6):
rtc: sun6i: Add sun6i RTC driver
rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc
ARM: dts: sun6i: add rtc device node
ARM: dts: sun8i: add rtc device node
ARM: sunxi: Add A31 RTC driver to sunxi_defconfig
ARM: sunxi: Add A31 RTC driver to multi_v7_defconfig
.../devicetree/bindings/rtc/sun6i-rtc.txt | 17 +
arch/arm/boot/dts/sun6i-a31.dtsi | 6 +
arch/arm/boot/dts/sun8i-a23.dtsi | 6 +
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/configs/sunxi_defconfig | 1 +
drivers/rtc/Kconfig | 9 +-
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-sun6i.c | 448 +++++++++++++++++++++
8 files changed, 488 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/rtc/sun6i-rtc.txt
create mode 100644 drivers/rtc/rtc-sun6i.c
--
2.0.1
^ permalink raw reply
* [PATCH 1/3] pinctrl: rockchip: set is_generic in pinconf_ops
From: Linus Walleij @ 2014-07-23 14:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <3086962.49c4Dnm508@diego>
On Sun, Jul 20, 2014 at 1:48 AM, Heiko St?bner <heiko@sntech.de> wrote:
> The rockchip pinctrl driver implements the generic pinconfig, therefore
> also state this, so that the default pinconf dump functions work.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/5] rtc: sun6i: Add sun6i RTC driver
From: Chen-Yu Tsai @ 2014-07-23 14:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140723095542.GN20328@lukather>
On Wed, Jul 23, 2014 at 5:55 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Mon, Jul 21, 2014 at 10:46:06PM +0800, Chen-Yu Tsai wrote:
>> Hi,
>>
>> On Fri, Jul 18, 2014 at 4:07 PM, Maxime Ripard
>> <maxime.ripard@free-electrons.com> wrote:
>> > Hi,
>> >
>> > On Mon, Jul 14, 2014 at 03:32:13PM +0800, Chen-Yu Tsai wrote:
>> >> This patch introduces the driver for the RTC in the Allwinner A31 and
>> >> A23 SoCs.
>> >>
>> >> Unlike the RTC found in A10/A20 SoCs, which was part of the timer, the
>> >> RTC in A31/A23 are a separate hardware block, which also contain a few
>> >> controls for the RTC block hardware (a regulator and RTC block GPIO pin
>> >> latches), while also having separate interrupts for the alarms.
>> >
>> > Do you plan on supporting those at some point?
>>
>> I haven't seen any devices use the regulator (which has an output pin).
>> I suppose we shouldn't add drivers for things we can't verify.
>> As for the GPIO pin latches, I'll have to experiment some more to figure
>> out what they do exactly.
>
> Ok.
>
>> > It's also worth noting that the first registers are supposed to
>> > control the source of the low frequency oscillator in the SoC, which
>> > will probably be the most troublesome, since we need these clocks very
>> > early on.
>>
>> That's true. I suppose the bootloader configures this. IIRC I've seen
>> code for this in boot0 or boot1 from Allwinner. I can't find the equivalent
>> for our sun4i u-boot though.
>
> Do you know what was the bootloader configuring it to?
I checked this some time ago, when I started to look at the sunxi clock code.
For all the devices (sun6/7/8i) I've checked, the system is configured to use
the external 32.768k oscillator.
> I don't really know how we can deal with this in a nice way, but I
> guess it's not so urgent.
I agree. I will look at the BROM (for sun4/7i) and boot0 (sun6i) for signs of
when it is configured. Then we can determine if we need to implement it
somewhere.
[...]
ChenYu
^ permalink raw reply
* [PATCH v2 1/3] usb: dwc3: add ST dwc3 glue layer to manage dwc3 HC
From: Peter Griffin @ 2014-07-23 14:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140722145711.GC20588@saruman.home>
Hi Felipe,
Thanks for reviewing, see my comments inline: -
> > > Just use {read,write}l_relaxed() directly.
> >
> > Ok, unabstracted in v3
>
> no, no... all other glues add their own local helpers for register
> access. This is good for tracing, it's very easy to add a tracepoint to
> this sort of function and get very low overhead tracing of every
> register access.
I've put the IO accessors back in for V3
> > They are just bit setting macros, I've converted them over to use BIT macro now,
> > so it no longer takes a parameter.
>
> the macros are better, but make them upper case as everybody else.
Fixed in v3.
> > I've asked ST how this value was derirved and why. It came from validation.
> > The docs don't mention that it is necessary, and removing it
> > seems to have no ill effects. So I've removed this udelay in v3.
>
> make sure to test with many, many iterations just to make sure.
Yes will do, I've been booting my board all day, and so far no failures.
> > Ok. Do the DT folks have any comment on this?
>
> look at the child's dr-mode property instead of adding your own.
Thanks for the hint, now using dr-mode binding in V3 :-)
>
> > > > + dwc3_data->glue_base = devm_request_and_ioremap(dev, res);
>
> use devm_ioremap_resource()
Fixed in V3
> > Your right, this was wrong. It was some legacy code which is
> > unnecessary and I've removed this in v3.
>
> if you're going for DT, why don't you create the parent and the child
> from DT as omap/exynos/qcom are doing ?
Now creating parent and child from DT like OMAP in v3
> > > > + reset_control_assert(dwc3_data->rstc_pwrdn);
> > > > +
> > > > + pinctrl_pm_select_sleep_state(dev);
>
> pinctrl will select sleep and default states automatically for you.
I've left this in v3, as greping around I couldn't see how that could happen automatically.
Also I just double checked with linusw on irc who confirmed that the only state which is
ever auto-selected is "default". All other states, as well as going back to default
state need to be explicitly called.
Hope thats ok.
regards,
Peter.
^ permalink raw reply
* [PATCH 13/11] arm64: Add support for 48-bit VA space with 64KB page configuration
From: Catalin Marinas @ 2014-07-23 14:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <619F8412-0992-4C87-AF55-83F70E605F7A@gmail.com>
On Wed, Jul 23, 2014 at 02:49:09PM +0100, Jungseok Lee wrote:
> On Jul 23, 2014, at 12:37 AM, Catalin Marinas wrote:
> > On Tue, Jul 22, 2014 at 04:13:27PM +0100, Jungseok Lee wrote:
> >> On Jul 22, 2014, at 00:09 +900 Catalin Marinas wrote:
> >>> This patch allows support for 3 levels of page tables with 64KB page
> >>> configuration allowing 48-bit VA space. The pgd is no longer a full
> >>> PAGE_SIZE (PTRS_PER_PGD is 64) and (swapper|idmap)_pg_dir are not fully
> >>> populated (pgd_alloc falls back to kzalloc).
> >>>
> >>> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> >>> ---
> >>
> >> One more step :)
> >
> > The last before the upcoming merging window. I also updated the
> > pgtable-4levels branch with the latest.
>
> I've tested the latest potable-4levels branch and 64KB + 3 Levels
> works fine on model.
>
> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
Thanks.
--
Catalin
^ permalink raw reply
* [PATCH v3] platform: Make platform_bus device a platform device
From: Pawel Moll @ 2014-07-23 14:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20140722221619.GA15781@kroah.com>
On Tue, 2014-07-22 at 23:16 +0100, Greg Kroah-Hartman wrote:
> On Tue, Jul 22, 2014 at 06:55:19PM +0100, Pawel Moll wrote:
> > ... describing the root of the device tree, so one can write
> > a platform driver initializing the platform.
> >
> > There has been a lot of references to platform_bus device where
> > it didn't make any sense, because simply using NULL as a parent
> > will make the device be adopted by the top level anyway.
> >
> > Signed-off-by: Pawel Moll <pawel.moll@arm.com>
> > ---
> > Changes since v2:
> >
> > * replaced references to platform_bus.dev with NULL
> > in places where it shouldn't make any difference
>
> How about split this up with just the "change to NULL" changes as one
> patch, and the rest as a second one?
Yes, was about to do exactly this.
Pawel
^ permalink raw reply
* [PATCH v3] platform: Make platform_bus device a platform device
From: Pawel Moll @ 2014-07-23 14:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMgya9i=zc_AVO_mgrC_FjYz-RWxwXguNueVA=7gpq=5sA@mail.gmail.com>
On Tue, 2014-07-22 at 20:46 +0100, Olof Johansson wrote:
> > @@ -946,12 +946,18 @@ int __init platform_bus_init(void)
> >
> > early_platform_cleanup();
> >
> > - error = device_register(&platform_bus);
> > + dev_set_name(&platform_bus.dev, "%s", platform_bus.name);
> > + error = device_register(&platform_bus.dev);
> > if (error)
> > return error;
> > error = bus_register(&platform_bus_type);
> > - if (error)
> > - device_unregister(&platform_bus);
> > + if (!error) {
> > + platform_bus.dev.of_node = of_allnodes;
>
> This breaks all non-OF platforms:
>
> drivers/base/platform.c: In function 'platform_bus_init':
> drivers/base/platform.c:955:30: error: 'of_allnodes' undeclared (first
> use in this function)
> platform_bus.dev.of_node = of_allnodes;
Right, of course, my bad. I can't see any other way of getting the tree
root, so an #ifdef it will be...
Thanks for pointing this out!
Pawe?
^ permalink raw reply
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