Re: [PATCH v5 5/6] arm64: dts: rockchip: add PWM nodes to RK3576 SoC dtsi

Damon Ding
2026-04-26T07:30:49Z

Hi Nicolas,

On 4/20/2026 9:52 PM, Nicolas Frattaroli wrote:
> The RK3576 SoC features three distinct PWM controllers, with variable
> numbers of channels. Add each channel as a separate node to the SoC's
> device tree, as they don't really overlap in register ranges.
>
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3576.dtsi | 208 +++++++++++++++++++++++++++++++
> 1 file changed, 208 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index e12a2a0cfb89..55d6b103c329 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1032,6 +1032,32 @@ uart1: serial@27310000 {
> status = "disabled";
> };
>
> + pwm0_2ch_0: pwm@27330000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x27330000 0x0 0x1000>;
> + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,
> + <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0m0_ch0>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm0_2ch_1: pwm@27331000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x27331000 0x0 0x1000>;
> + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,
> + <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0m0_ch1>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> pmu: power-management@27380000 {
> compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
> reg = <0x0 0x27380000 0x0 0x800>;
> @@ -2630,6 +2656,188 @@ uart9: serial@2adc0000 {
> status = "disabled";
> };
>
> + pwm1_6ch_0: pwm@2add0000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add0000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch0>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_1: pwm@2add1000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add1000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch1>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_2: pwm@2add2000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add2000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch2>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_3: pwm@2add3000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add3000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch3>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_4: pwm@2add4000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add4000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch4>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_5: pwm@2add5000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add5000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch5>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_0: pwm@2ade0000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade0000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch0>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_1: pwm@2ade1000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade1000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch1>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_2: pwm@2ade2000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade2000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch2>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_3: pwm@2ade3000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade3000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch3>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_4: pwm@2ade4000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade4000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch4>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_5: pwm@2ade5000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade5000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch5>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_6: pwm@2ade6000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade6000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch6>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_7: pwm@2ade7000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade7000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch7>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> saradc: adc@2ae00000 {
> compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
> reg = <0x0 0x2ae00000 0x0 0x10000>;
>

According to the RK3576 TRM, the register base address, clocks and
interrupt configuration of the PWM node are all correct

Reviewed-by: Damon Ding <damon.ding@rock-chips.com>

Best regards,
Damon