[PATCH 2/2] arm: invalidate TLBs when enabling mmu

[eric.y.miao@gmail.com (Eric Miao)]

On Wed, Mar 10, 2010 at 12:45 AM, Catalin Marinas
<catalin.marinas@arm.com> wrote:
> On Tue, 2010-03-09 at 14:07 +0000, Saeed Bishara wrote:
>> Signed-off-by: Saeed Bishara <saeed@marvell.com>
>> ---
>> ?arch/arm/boot/compressed/head.S | ? ?1 +
>> ?1 files changed, 1 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/compressed/head.S
>> b/arch/arm/boot/compressed/head.S
>> index 4fddc50..a1ab79f 100644
>> --- a/arch/arm/boot/compressed/head.S
>> +++ b/arch/arm/boot/compressed/head.S
>> @@ -489,6 +489,7 @@ __armv7_mmu_cache_on:
>> ? ? ? ? ? ? ? ? mcr ? ? p15, 0, r0, c1, c0, 0 ? @ load control
>> register
>> ? ? ? ? ? ? ? ? mrc ? ? p15, 0, r0, c1, c0, 0 ? @ and read it back
>> ? ? ? ? ? ? ? ? mov ? ? r0, #0
>> + ? ? ? ? ? ? ? mcr ? ? p15, 0, r0, c8, c7, 0 ? @ invalidate I,D TLBs
>> ? ? ? ? ? ? ? ? mcr ? ? p15, 0, r0, c7, c5, 4 ? @ ISB
>> ? ? ? ? ? ? ? ? mov ? ? pc, r12
>
> The TLB invalidating is done earlier in the __armv7_mmu_cache_on
> function, why do you need to do it again?
>

Well, the only difference between these two "invalidate"s looks like one is
before control register load and one after.

We do have the problem of slow decompressing when this invalidate
change is not there. I do suspect this might be Dove specific. But yet,
Catalin, could you confirm the behavior difference of "invalidate" before
and after MMU is actaully turned on?