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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa5998e64c4sm190708566b.97.2024.11.29.08.56.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 29 Nov 2024 08:56:11 -0800 (PST) Message-ID: <00941d91-7366-4836-9d3a-7e505528a4e8@oss.qualcomm.com> Date: Fri, 29 Nov 2024 17:56:09 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/7] drm/msm: adreno: dynamically generate GMU bw table To: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20241128-topic-sm8x50-gpu-bw-vote-v3-0-81d60c10fb73@linaro.org> <20241128-topic-sm8x50-gpu-bw-vote-v3-3-81d60c10fb73@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241128-topic-sm8x50-gpu-bw-vote-v3-3-81d60c10fb73@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: f4ovB-1_7fvWIb29saxpa5fOoEh0Rfkf X-Proofpoint-ORIG-GUID: f4ovB-1_7fvWIb29saxpa5fOoEh0Rfkf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 phishscore=0 adultscore=0 spamscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2411290136 On 28.11.2024 11:25 AM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale the ddr > bandwidth along the frequency and power domain level, but for > now we statically fill the bw_table with values from the > downstream driver. > > Only the first entry is used, which is a disable vote, so we > currently rely on scaling via the linux interconnect paths. > > Let's dynamically generate the bw_table with the vote values > previously calculated from the OPPs. > > Those entried will then be used by the GMU when passing the entries > appropriate bandwidth level while voting for a gpu frequency. > > Signed-off-by: Neil Armstrong > --- [...] > drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 39 ++++++++++++++++++++++++++++++++--- > 1 file changed, 36 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > index cb8844ed46b29c4569d05eb7a24f7b27e173190f..fe1946650425b749bad483dad1e630bc8be83abc 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > @@ -621,6 +621,35 @@ static void a740_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) > msg->cnoc_cmds_data[1][0] = 0x60000001; > } > > +static void a740_generate_bw_table(const struct a6xx_info *info, struct a6xx_gmu *gmu, > + struct a6xx_hfi_msg_bw_table *msg) This should work for all targets > +{ > + unsigned int i, j; > + > + msg->ddr_wait_bitmask = 0x7; GENMASK; also should be generated based on BCM data dynamically, there's logic for it in bcm-voter.c : tcs_list_gen() > + > + for (i = 0; i < GMU_MAX_BCMS; i++) { > + if (!info->bcms[i].name) > + break; > + msg->ddr_cmds_addrs[i] = cmd_db_read_addr(info->bcms[i].name); A7xx share a common list of BCMs, the buswidth may differ per soc and it's something already stored in ICC drivers > + } > + msg->ddr_cmds_num = i; > + > + for (i = 0; i < gmu->nr_gpu_bws; ++i) > + for (j = 0; j < msg->ddr_cmds_num; j++) > + msg->ddr_cmds_data[i][j] = gmu->gpu_ib_votes[i][j]; > + msg->bw_level_num = gmu->nr_gpu_bws; > + > + /* TODO also generate CNOC commands */ We only do on/off (0/100 units - kbps?), it seems > + > + msg->cnoc_cmds_num = 1; > + msg->cnoc_wait_bitmask = 0x1; > + > + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); > + msg->cnoc_cmds_data[0][0] = 0x40000000; > + msg->cnoc_cmds_data[1][0] = 0x60000001; > +} > + > static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) > { > /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */ > @@ -664,6 +693,7 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) > struct a6xx_hfi_msg_bw_table *msg; > struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); > struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; > + const struct a6xx_info *info = adreno_gpu->info->a6xx; > > if (gmu->bw_table) > goto send; > @@ -690,9 +720,12 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) > a690_build_bw_table(msg); > else if (adreno_is_a730(adreno_gpu)) > a730_build_bw_table(msg); > - else if (adreno_is_a740_family(adreno_gpu)) > - a740_build_bw_table(msg); > - else > + else if (adreno_is_a740_family(adreno_gpu)) { > + if (info->bcms && gmu->nr_gpu_bws > 1) > + a740_generate_bw_table(info, gmu, msg); This if should come before the hardcoded if-else chain, as it applies to all platforms Konrad