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Wed, 23 Apr 2025 02:46:59 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 53N2kwlE027965 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 23 Apr 2025 02:46:58 GMT Received: from [10.71.110.123] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 22 Apr 2025 19:46:57 -0700 Message-ID: <0101602d-0434-47ea-8957-471c4ead100d@quicinc.com> Date: Tue, 22 Apr 2025 19:46:57 -0700 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] dt-bindings: display/msm: add stream 1 pixel clock binding To: Dmitry Baryshkov CC: Rob Clark , Sean Paul , "Marijn Suijten" , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Mahadevan , , , , , References: <20241202-dp_mst_bindings-v1-0-9a9a43b0624a@quicinc.com> <20241202-dp_mst_bindings-v1-3-9a9a43b0624a@quicinc.com> Content-Language: en-US From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: N6P4BI9iBoWI2e6EKSWBzyIelS0nFBu_ X-Proofpoint-ORIG-GUID: N6P4BI9iBoWI2e6EKSWBzyIelS0nFBu_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDAxNiBTYWx0ZWRfX7V0xOTEPtjlF sEvkFxHMzaUNx5nLps0q7Tuv3zlFoXSnKrd9j5MJaIXD5oXrLyfN4o5GtduD4J2ALQuk5QmVV4b 67ZU6yFrY5BErSWR/ExbBTC8QVusgVhX37xy0QU3vYSXuFgf3d9fqoZUto2nYWzhyPMzIW/5cLy ON3iowNneAIjqWRq5WLMWbBsA3IJx6eHzsnxw167FKIqCKlX9c37CQN6zEEcErPICO1gKTwYy+J H+HODBlzdsnv1ZPIqPEZ3gOFXqqVualKNHvL/T40HDVOscotFWih7iCTRK4vX6oR2ouH8kOV6ui ob4z9cOL9t+qJijDVS7IUkNtHVFHasp4/10jBZ6pjwwApA/ek5Uo9c7RN8OO5AKyF8GfoKFsmSY LAw63daouEbixRMN9Scf7hrD8eA+HY0Ao9B5TqD6rItoo0kSfvfIGu9XE2BaUoNMs0CCkgZd X-Authority-Analysis: v=2.4 cv=ZpjtK87G c=1 sm=1 tr=0 ts=680854a3 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=zCC9CgH-0czqcsUVom0A:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-23_01,2025-04-22_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 mlxlogscore=999 spamscore=0 impostorscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230016 On 12/3/2024 5:43 AM, Dmitry Baryshkov wrote: > On Mon, Dec 02, 2024 at 07:31:41PM -0800, Abhinav Kumar wrote: >> On some chipsets the display port controller can support more >> than one pixel stream (multi-stream transport). To support MST >> on such chipsets, add the binding for stream 1 pixel clock for >> display port controller. Since this mode is not supported on all >> chipsets, add exception rules and min/max items to clearly mark >> which chipsets support only SST mode (single stream) and which ones >> support MST. >> >> Signed-off-by: Abhinav Kumar >> --- >> .../bindings/display/msm/dp-controller.yaml | 32 ++++++++++++++++++++++ >> .../bindings/display/msm/qcom,sa8775p-mdss.yaml | 9 ++++-- >> 2 files changed, 38 insertions(+), 3 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml >> index 9fe2bf0484d8..650d19e58277 100644 >> --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml >> +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml >> @@ -50,30 +50,38 @@ properties: >> maxItems: 1 >> >> clocks: >> + minItems: 5 >> items: >> - description: AHB clock to enable register access >> - description: Display Port AUX clock >> - description: Display Port Link clock >> - description: Link interface clock between DP and PHY >> - description: Display Port stream 0 Pixel clock >> + - description: Display Port stream 1 Pixel clock >> >> clock-names: >> + minItems: 5 >> items: >> - const: core_iface >> - const: core_aux >> - const: ctrl_link >> - const: ctrl_link_iface >> - const: stream_pixel >> + - const: stream_1_pixel >> >> assigned-clocks: >> + minItems: 2 >> items: >> - description: link clock source >> - description: stream 0 pixel clock source >> + - description: stream 1 pixel clock source >> >> assigned-clock-parents: >> + minItems: 2 >> items: >> - description: Link clock PLL output provided by PHY block >> - description: Stream 0 pixel clock PLL output provided by PHY block >> + - description: Stream 1 pixel clock PLL output provided by PHY block >> >> phys: >> maxItems: 1 >> @@ -175,6 +183,30 @@ allOf: >> required: >> - "#sound-dai-cells" >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,sa8775p-dp > > Why do you need an extra platform conditional? > I expect this list to grow and also there can be chipsets which support 4 streams as well, so an extra platform conditional was needed. >> + >> + then: >> + properties: >> + clocks: >> + maxItems: 6 >> + clock-names: >> + items: >> + - const: core_iface >> + - const: core_aux >> + - const: ctrl_link >> + - const: ctrl_link_iface >> + - const: stream_pixel >> + - const: stream_1_pixel >> + assigned-clocks: >> + maxItems: 3 >> + assigned-clock-parents: >> + maxItems: 3 >> + >> additionalProperties: false >> >> examples: >> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml >> index 58f8a01f29c7..7f10e6ad8f63 100644 >> --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml >> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml >> @@ -177,16 +177,19 @@ examples: >> <&dispcc_dptx0_aux_clk>, >> <&dispcc_dptx0_link_clk>, >> <&dispcc_dptx0_link_intf_clk>, >> - <&dispcc_dptx0_pixel0_clk>; >> + <&dispcc_dptx0_pixel0_clk>, >> + <&dispcc_dptx0_pixel1_clk>; >> clock-names = "core_iface", >> "core_aux", >> "ctrl_link", >> "ctrl_link_iface", >> - "stream_pixel"; >> + "stream_pixel", >> + "stream_1_pixel"; >> >> assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, >> + <&dispcc_mdss_dptx0_pixel1_clk_src>, >> <&dispcc_mdss_dptx0_pixel0_clk_src>; >> - assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>; >> + assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>, <&mdss0_edp_phy 1>; >> >> phys = <&mdss0_edp_phy>; >> phy-names = "dp"; >> >> -- >> 2.34.1 >> >