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([2a01:e0a:3d9:2080:e7a:79e6:53ed:ce35]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b42a908d3sm44412925e9.22.2025.08.19.06.30.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Aug 2025 06:30:07 -0700 (PDT) Message-ID: <0257f893-fed8-4ee9-ad4e-cdcdad8b5c85@linaro.org> Date: Tue, 19 Aug 2025 15:30:06 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Reply-To: Neil Armstrong Subject: Re: [PATCH V4 4/4] arm64: dts: qcom: sm8550: Remove SDR104/SDR50 broken capabilities To: Sarthak Garg , Konrad Dybcio , Krzysztof Kozlowski , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Adrian Hunter Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_cang@quicinc.com, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, kernel@oss.qualcomm.com References: <20250801084518.2259767-1-quic_sartgarg@quicinc.com> <20250801084518.2259767-5-quic_sartgarg@quicinc.com> <69f2807c-9a28-4b31-97cc-2756f0ab9fd4@kernel.org> <8b023e56-435b-43df-8b15-c562a494e06f@kernel.org> <4091c488-996c-4318-82ad-c054a9ef5a22@oss.qualcomm.com> From: Neil Armstrong Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 14/08/2025 09:15, Sarthak Garg wrote: > > > On 8/13/2025 5:37 PM, Konrad Dybcio wrote: >> On 8/13/25 1:56 PM, Krzysztof Kozlowski wrote: >>> On 13/08/2025 13:21, Konrad Dybcio wrote: >>>> On 8/13/25 1:08 PM, Sarthak Garg wrote: >>>>> >>>>> >>>>> On 8/5/2025 2:55 PM, Krzysztof Kozlowski wrote: >>>>>> On 05/08/2025 11:19, Sarthak Garg wrote: >>>>>>> >>>>>>> >>>>>>> On 8/1/2025 2:32 PM, Krzysztof Kozlowski wrote: >>>>>>>> On 01/08/2025 10:45, Sarthak Garg wrote: >>>>>>>>> The kernel now handles level shifter limitations affecting SD card >>>>>>>>> modes, making it unnecessary to explicitly disable SDR104 and SDR50 >>>>>>>>> capabilities in the device tree. >>>>>>>>> >>>>>>>>> However, due to board-specific hardware constraints particularly related >>>>>>>>> to level shifter in this case the maximum frequency for SD High-Speed >>>>>>>>> (HS) mode must be limited to 37.5 MHz to ensure reliable operation of SD >>>>>>>>> card in HS mode. This is achieved using the max-sd-hs-frequency property >>>>>>>>> in the board DTS. >>>>>>>>> >>>>>>>>> Signed-off-by: Sarthak Garg >>>>>>>>> --- >>>>>>>>>     arch/arm64/boot/dts/qcom/sm8550-hdk.dts                     | 1 + >>>>>>>>>     arch/arm64/boot/dts/qcom/sm8550-mtp.dts                     | 1 + >>>>>>>>>     arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 1 + >>>>>>>>>     arch/arm64/boot/dts/qcom/sm8550.dtsi                        | 3 --- >>>>>>>>>     4 files changed, 3 insertions(+), 3 deletions(-) >>>>>>>>> >>>>>>>> >>>>>>>> This will break MMC for all of the users and nothing in commit msg or >>>>>>>> cover letter explains that or mentions merging strategy. >>>>>>>> >>>>>>>> Exactly this case is covered by your internal guideline, no? Please read it. >>>>>>>> >>>>>>>> Best regards, >>>>>>>> Krzysztof >>>>>>> >>>>>>> Just to make sure I’m addressing the right concern — are you primarily >>>>>>> worried about the introduction of the max-sd-hs-frequency property in >>>>>>> the board DTS files, or about the removal of the sdhci-caps-mask >>>>>>> from the common sm8550.dtsi? >>>>>> >>>>>> >>>>>> Apply this patch and test MMC. Does it work? No. Was it working? Yes. >>>>>> >>>>>> >>>>>> Best regards, >>>>>> Krzysztof >>>>> >>>>> >>>>> You're absolutely right to raise the concern about potential breakage. >>>>> After conducting additional testing across multiple boards, I’ve confirmed that the removal of SDR104/SDR50 broken capabilities does indeed affect V1 SM8550 devices. >>>> >>>> v1 is a prototype revision, please forget it exists, we most definitely >>>> do not support it upstream >>> >>> >>> You should double check. SM8450 (not v1!) needed it, so either it was >>> copied to SM8550 (v2!) by mistake or was also needed. >> >> I believe that the speed capabilities are indeed restricted on 8550-final >> and that's why this patchset exists in the first place >> >> Konrad > > Hi Krzysztof, Konrad, > > Konrad is right — this patch series addresses limitations seen on > SM8550-final silicon. > > SDR50 mode: The tuning support introduced in this series helps ensure > reliable operation. > SDR104 mode: limitations are resolved in SM8550 v2. I guess the state is the same for SM8650, it also requires the max-sd-hs-frequency. I guess all boards with a level-shifter on board would need such limitation, including most of the HDK boards (SM8450 included) Neil > > But still to avoid regressions, *I’ll like to retain sdhci-caps-mask in > sm8550.dtsi for now and revisit its removal for future targets after > thorough validation and testing from the beginning.* > > Konrad suggested placing max-sd-hs-frequency in the SoC dtsi. > Krzysztof, could you please share your thoughts on this approach? > > Best regards, > Sarthak Garg