From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Jie Gan <jie.gan@oss.qualcomm.com>,
Mike Leach <mike.leach@arm.com>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v14 2/7] coresight: tmc: add create/clean functions for etr_buf_list
Date: Mon, 9 Mar 2026 10:02:09 +0000 [thread overview]
Message-ID: <03705fdb-e13d-4b5b-8ee4-af9348469b42@arm.com> (raw)
In-Reply-To: <20260309-enable-byte-cntr-for-ctcu-v14-2-c08823e5a8e6@oss.qualcomm.com>
On 09/03/2026 09:47, Jie Gan wrote:
> Introduce functions for creating and inserting or removing the
> etr_buf_node to/from the etr_buf_list.
>
> The byte-cntr functionality requires two etr_buf to receive trace data.
> The active etr_buf collects the trace data from source device, while the
> byte-cntr reading function accesses the deactivated etr_buf after is
> has been filled and synced, transferring data to the userspace.
>
> Reviewed-by: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> drivers/hwtracing/coresight/coresight-tmc-core.c | 1 +
> drivers/hwtracing/coresight/coresight-tmc-etr.c | 94 ++++++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tmc.h | 17 +++++
> 3 files changed, 112 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
> index c89fe996af23..bac3278ef4dd 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
> @@ -835,6 +835,7 @@ static int __tmc_probe(struct device *dev, struct resource *res)
> idr_init(&drvdata->idr);
> mutex_init(&drvdata->idr_mutex);
> dev_list = "tmc_etr";
> + INIT_LIST_HEAD(&drvdata->etr_buf_list);
> break;
> case TMC_CONFIG_TYPE_ETF:
> desc.groups = coresight_etf_groups;
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 4dc1defe27a5..15c0874ff641 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -1918,6 +1918,100 @@ const struct coresight_ops tmc_etr_cs_ops = {
> .panic_ops = &tmc_etr_sync_ops,
> };
>
> +/**
> + * tmc_clean_etr_buf_list - clean the etr_buf_list.
> + * @drvdata: driver data of the TMC device.
> + *
> + * Remove the allocated node from the list and free the extra buffer.
> + */
> +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata)
> +{
...
> +}
> +EXPORT_SYMBOL_GPL(tmc_clean_etr_buf_list);
> +
> +/**
> + * tmc_create_etr_buf_list - create a list to manage the etr_buf_node.
> + * @drvdata: driver data of the TMC device.
> + * @num_nodes: number of nodes want to create with the list.
> + *
> + * Return 0 upon success and return the error number if fail.
> + */
> +int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes)
> +{
...
> +EXPORT_SYMBOL_GPL(tmc_create_etr_buf_list);
Given the above functions are "EXPORTED" please could you make sure that
the locking requirements are documented and asserted (lockdep_assert)
in the functions ?
Suzuki
> +
> int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
> {
> int ret = 0;
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 319a354ede9f..5ac07e8dd5ff 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -208,6 +208,19 @@ struct tmc_resrv_buf {
> s64 len;
> };
>
> +/**
> + * @sysfs_buf: Allocated sysfs_buf.
> + * @is_free: Indicates whether the buffer is free to choose.
> + * @pos: Position of the buffer.
> + * @node: Node in etr_buf_list.
> + */
> +struct etr_buf_node {
> + struct etr_buf *sysfs_buf;
> + bool is_free;
> + loff_t pos;
> + struct list_head node;
> +};
> +
> /**
> * struct tmc_drvdata - specifics associated to an TMC component
> * @atclk: optional clock for the core parts of the TMC.
> @@ -245,6 +258,7 @@ struct tmc_resrv_buf {
> * (after crash) by default.
> * @crash_mdata: Reserved memory for storing tmc crash metadata.
> * Used by ETR/ETF.
> + * @etr_buf_list: List that is used to manage allocated etr_buf.
> */
> struct tmc_drvdata {
> struct clk *atclk;
> @@ -275,6 +289,7 @@ struct tmc_drvdata {
> struct etr_buf *perf_buf;
> struct tmc_resrv_buf resrv_buf;
> struct tmc_resrv_buf crash_mdata;
> + struct list_head etr_buf_list;
> };
>
> struct etr_buf_operations {
> @@ -447,5 +462,7 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev,
> enum cs_mode mode,
> struct coresight_path *path);
> extern const struct attribute_group coresight_etr_group;
> +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata);
> +int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes);
>
> #endif
>
next prev parent reply other threads:[~2026-03-09 10:03 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-09 9:47 [PATCH v14 0/7] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2026-03-09 9:47 ` [PATCH v14 1/7] coresight: core: refactor ctcu_get_active_port and make it generic Jie Gan
2026-03-09 9:47 ` [PATCH v14 2/7] coresight: tmc: add create/clean functions for etr_buf_list Jie Gan
2026-03-09 10:02 ` Suzuki K Poulose [this message]
2026-03-09 10:27 ` Jie Gan
2026-03-09 9:47 ` [PATCH v14 3/7] coresight: tmc: introduce tmc_sysfs_ops to wrap sysfs read operations Jie Gan
2026-03-09 9:47 ` [PATCH v14 4/7] coresight: etr: add a new function to retrieve the CTCU device Jie Gan
2026-03-09 9:47 ` [PATCH v14 5/7] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2026-03-09 9:47 ` [PATCH v14 6/7] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2026-03-09 12:43 ` Suzuki K Poulose
2026-03-10 3:01 ` Jie Gan
2026-03-10 9:15 ` Suzuki K Poulose
2026-03-10 10:58 ` Jie Gan
2026-03-11 8:02 ` Jie Gan
2026-03-09 9:47 ` [PATCH v14 7/7] arm64: dts: qcom: lemans: add interrupts to CTCU device Jie Gan
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