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Mon, 04 May 2026 03:34:21 -0700 (PDT) X-Received: by 2002:a17:902:ed0a:b0:2b9:87e0:1f80 with SMTP id d9443c01a7336-2b9f25e667emr65107105ad.24.1777890860821; Mon, 04 May 2026 03:34:20 -0700 (PDT) Received: from [10.218.50.10] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b9caa8c3f2sm120191565ad.4.2026.05.04.03.34.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 May 2026 03:34:20 -0700 (PDT) Message-ID: <05346f88-4ffe-495a-af0e-ff5e0371c03c@oss.qualcomm.com> Date: Mon, 4 May 2026 16:04:14 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] thermal: qcom: tsens: atomic temperature read with hardware-guided retries To: Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba Cc: linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, manaf.pallikunhi@oss.qualcomm.com References: <20260430054422.2461150-1-priyansh.jain@oss.qualcomm.com> <20260430054422.2461150-2-priyansh.jain@oss.qualcomm.com> <10c07347-a0df-42d3-b216-5150817b9ed2@oss.qualcomm.com> Content-Language: en-US From: Priyansh Jain In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA0MDExMiBTYWx0ZWRfX5UxeuQ/KSDrU N4zIFGeeF2TPuw+6iwZKEdJT74tosAJPVVbD7HuWqaXHdH8KZlsQmiHRcoLGifLZXL2dU8XLouZ vfh0hQXkZCMQuTkHM2maFAOqi5feKu7OF+97bThpGLOhVQMDF6lsg08fTyssjfcGBUPZltUaXhb SP9ewcDm81DzOy7S6Xltfy984rsbmGfTpsk2V4fNNHcfxRZqQ0o1MiNOuolBS4tOaPmbWJlJs5L WIUHWzmEadsfhYJPm+cGSC5jE3Q2K2Kiy9C4sN1f2RkqosGQFu+PzNU1ZnrIcYx/8nZTz92Ti4H 3QalxhAHadd2bkOnPDPUFVCmn0QldeMsIvHbybH56YXr3dnd8J9gtDW4cZ1D8JVnw+YHVGzp3WN 8i0ZSH7geVWT8qSZjijwaA5QxDl8A4g0YhmMqHuludrO7gREdK2vPkhBr4p/P2qxVcDhA2LSnmA Hf6zA7dGD+j6TexIqYQ== X-Proofpoint-ORIG-GUID: ZsCGXfK2xOfdkyYy14Sj5HJwiQu7X5Up X-Proofpoint-GUID: ZsCGXfK2xOfdkyYy14Sj5HJwiQu7X5Up X-Authority-Analysis: v=2.4 cv=C47ZDwP+ c=1 sm=1 tr=0 ts=69f8762e cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=gIxJPFuM_M9iIqC3imoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-04_03,2026-04-30_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605040112 On 04-05-2026 03:29 pm, Konrad Dybcio wrote: > On 5/4/26 11:42 AM, Priyansh Jain wrote: >> >> On 30-04-2026 09:21 pm, Konrad Dybcio wrote: >>> On 4/30/26 7:44 AM, Priyansh Jain wrote: >>>> The existing TSENS temperature read logic polls the valid bit and then >>>> reads the temperature register. When temperature reads are triggered >>>> at very short intervals, this can race with hardware updates and allow >>>> the temperature field to be read while it is still being updated. >>>> >>>> In this case, the valid bit may already be asserted even though the >>>> temperature value is transitioning, resulting in an incorrect reading. >>>> >>>> Hardware programming guidelines require the temperature value and the >>>> valid bit to be sampled atomically in the same read transaction. A >>>> reading is considered valid only if the valid bit is observed set in >>>> that same sample. >>>> >>>> The guidelines further specify that software should attempt the >>>> temperature read up to three times to account for transient update >>>> windows. If none of the attempts observe a valid sample, a stable >>>> fallback value must be returned: if the first and second samples match, >>>> the second value is returned; otherwise, if the second and third >>>> samples match, the third value is returned. >>>> >>>> Update the TSENS sensor read logic to implement atomic sampling along >>>> with the recommended retry-and-compare fallback behavior. This removes >>>> the race window and ensures deterministic temperature values in >>>> accordance with hardware requirements. >>>> >>>> Signed-off-by: Priyansh Jain >>>> --- > > [...] > >>>> @@ -125,8 +128,7 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { >>>>       [WDOG_BARK_COUNT]  = REG_FIELD(TM_WDOG_LOG_OFF,             0,  7), >>>>         /* Sn_STATUS */ >>>> -    REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP,       TM_Sn_STATUS_OFF,  0,  11), >>>> -    REG_FIELD_FOR_EACH_SENSOR16(VALID,           TM_Sn_STATUS_OFF, 21,  21), >>>> +    REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP,       TM_Sn_STATUS_OFF,  0,  21), >>> ..this change feels rather odd - the existing regfields seem like a good >>> place to handle this register map difference >> This change is required to ensure that both the VALID bit and LAST_TEMP >> are read as part of a single transaction, in order to avoid a race condition where >> the VALID bit may already be asserted while the temperature value is still transitioning, >> potentially resulting in an incorrect reading. If needed, I can rename the field from >> LAST_TEMP to something that more clearly reflects a combined representation >> of the temperature value and the VALID bit. >> >> Let me know you thoughts on this. > > Hm, I somehow managed to skip the connection between the two.. > > I think we could retain the current (pretty good) containment of all > register differences between the versions as-is, with something like > this diff: > > - ret = regmap_field_read(priv->rf[field], &status); > + /* Fields within the STATUS register are only valid if read atomically */ > + ret = regmap_read(priv->rf[field].reg, &status); > if (ret) > return ret; > > and then falling back to the prior definitions of the VALID mask etc. Thanks for this feedback , this seems correct approach, i will update as per the suggestion provided Thanks, Priyansh > > Konrad