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[83.9.31.184]) by smtp.gmail.com with ESMTPSA id d13-20020a056512368d00b0049478cc4eb9sm2194621lfs.230.2022.12.27.03.48.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Dec 2022 03:48:57 -0800 (PST) Message-ID: <055fd005-13d4-ecc8-ab54-7638bd41be26@linaro.org> Date: Tue, 27 Dec 2022 12:48:54 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [RFC PATCH 04/12] clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20221227013225.2847382-1-dmitry.baryshkov@linaro.org> <20221227013225.2847382-5-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20221227013225.2847382-5-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 27.12.2022 02:32, Dmitry Baryshkov wrote: > Use ARRAY_SIZE() instead of manually specifying num_parents. This makes > adding/removing entries to/from parent_data easy and errorproof. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad > drivers/clk/qcom/gcc-apq8084.c | 136 ++++++++++++++++----------------- > 1 file changed, 68 insertions(+), 68 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c > index ab088d702d7c..b41f55b289ae 100644 > --- a/drivers/clk/qcom/gcc-apq8084.c > +++ b/drivers/clk/qcom/gcc-apq8084.c > @@ -132,7 +132,7 @@ static struct clk_rcg2 config_noc_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "config_noc_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -144,7 +144,7 @@ static struct clk_rcg2 periph_noc_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "periph_noc_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -156,7 +156,7 @@ static struct clk_rcg2 system_noc_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "system_noc_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -231,7 +231,7 @@ static struct clk_rcg2 ufs_axi_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "ufs_axi_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -250,7 +250,7 @@ static struct clk_rcg2 usb30_master_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "usb30_master_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -269,7 +269,7 @@ static struct clk_rcg2 usb30_sec_master_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "usb30_sec_master_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -322,7 +322,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup1_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -347,7 +347,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup1_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -360,7 +360,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup2_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -374,7 +374,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup2_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -387,7 +387,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup3_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -401,7 +401,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup3_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -414,7 +414,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup4_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -428,7 +428,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup4_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -441,7 +441,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup5_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -455,7 +455,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup5_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -468,7 +468,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup6_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -482,7 +482,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_qup6_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -515,7 +515,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_uart1_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -529,7 +529,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_uart2_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -543,7 +543,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_uart3_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -557,7 +557,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_uart4_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -571,7 +571,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_uart5_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -585,7 +585,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp1_uart6_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -598,7 +598,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup1_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -612,7 +612,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup1_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -625,7 +625,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup2_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -639,7 +639,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup2_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -652,7 +652,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup3_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -666,7 +666,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup3_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -679,7 +679,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup4_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -693,7 +693,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup4_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -706,7 +706,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup5_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -720,7 +720,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup5_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -733,7 +733,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup6_i2c_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -747,7 +747,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_qup6_spi_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -761,7 +761,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_uart1_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -775,7 +775,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_uart2_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -789,7 +789,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_uart3_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -803,7 +803,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_uart4_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -817,7 +817,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_uart5_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -831,7 +831,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "blsp2_uart6_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -852,7 +852,7 @@ static struct clk_rcg2 ce1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "ce1_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -873,7 +873,7 @@ static struct clk_rcg2 ce2_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "ce2_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -894,7 +894,7 @@ static struct clk_rcg2 ce3_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "ce3_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -915,7 +915,7 @@ static struct clk_rcg2 gp1_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "gp1_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -929,7 +929,7 @@ static struct clk_rcg2 gp2_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "gp2_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -943,7 +943,7 @@ static struct clk_rcg2 gp3_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "gp3_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -962,7 +962,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "pcie_0_aux_clk_src", > .parent_names = gcc_xo_pcie_sleep, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep), > .ops = &clk_rcg2_ops, > }, > }; > @@ -976,7 +976,7 @@ static struct clk_rcg2 pcie_1_aux_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "pcie_1_aux_clk_src", > .parent_names = gcc_xo_pcie_sleep, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_pcie_sleep), > .ops = &clk_rcg2_ops, > }, > }; > @@ -995,7 +995,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "pcie_0_pipe_clk_src", > .parent_names = gcc_xo_pcie, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_pcie), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1008,7 +1008,7 @@ static struct clk_rcg2 pcie_1_pipe_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "pcie_1_pipe_clk_src", > .parent_names = gcc_xo_pcie, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_pcie), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1026,7 +1026,7 @@ static struct clk_rcg2 pdm2_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "pdm2_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1046,7 +1046,7 @@ static struct clk_rcg2 sata_asic0_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "sata_asic0_clk_src", > .parent_names = gcc_xo_sata_asic0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_sata_asic0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1066,7 +1066,7 @@ static struct clk_rcg2 sata_pmalive_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "sata_pmalive_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1086,7 +1086,7 @@ static struct clk_rcg2 sata_rx_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "sata_rx_clk_src", > .parent_names = gcc_xo_sata_rx, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_sata_rx), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1104,7 +1104,7 @@ static struct clk_rcg2 sata_rx_oob_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "sata_rx_oob_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1131,7 +1131,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "sdcc1_apps_clk_src", > .parent_names = gcc_xo_gpll0_gpll4, > - .num_parents = 3, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4), > .ops = &clk_rcg2_floor_ops, > }, > }; > @@ -1145,7 +1145,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "sdcc2_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_floor_ops, > }, > }; > @@ -1159,7 +1159,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "sdcc3_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_floor_ops, > }, > }; > @@ -1173,7 +1173,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "sdcc4_apps_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_floor_ops, > }, > }; > @@ -1192,7 +1192,7 @@ static struct clk_rcg2 tsif_ref_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "tsif_ref_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1210,7 +1210,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "usb30_mock_utmi_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1228,7 +1228,7 @@ static struct clk_rcg2 usb30_sec_mock_utmi_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "usb30_sec_mock_utmi_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1246,7 +1246,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "usb_hs_system_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1312,7 +1312,7 @@ static struct clk_rcg2 usb_hsic_io_cal_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "usb_hsic_io_cal_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 1, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1347,7 +1347,7 @@ static struct clk_rcg2 usb_hsic_mock_utmi_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "usb_hsic_mock_utmi_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 1, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > }; > @@ -1365,7 +1365,7 @@ static struct clk_rcg2 usb_hsic_system_clk_src = { > .clkr.hw.init = &(struct clk_init_data){ > .name = "usb_hsic_system_clk_src", > .parent_names = gcc_xo_gpll0, > - .num_parents = 2, > + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), > .ops = &clk_rcg2_ops, > }, > };