From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C00F30E0CC for ; Thu, 16 Oct 2025 08:59:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760605186; cv=none; b=u4eMNuJOt28SqfrCO0MOOByo0ZLd3EUfdvmbDMabrdWvJ32oMhcwu5c3658fUc/skO/PKaQywUfXXJ3U4itA8Ph4zdG/EL7HE2+otziJeHaKNW3Gb1CccxLhWHj7QlgQwfUZmOALFSKrd2PoX4SUz9OTkTWuFFF5OTQPTy7yH40= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760605186; c=relaxed/simple; bh=WNY5WeFs7L6NX3cz5T0OqHmpqUTkL7fyS1R5p8Y5iSo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=UOHFEb2rxinU+lOq7lxDvmZGCwoHlg8fsO9u+ouM8zwDgyj9hnNaudPBl7yuqCp8FQVS9EdePKQ/DbFfssSdb6Rtp8VYeyc9pAE2QnTKbluNYu1RsN9H6g9/sDzoZ1j+43JTdxZ7ZJzuwPmSefmIUcF21vfMrZg6zgQp/Z0dmoc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=lAUdPufm; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="lAUdPufm" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-421851bca51so384509f8f.1 for ; Thu, 16 Oct 2025 01:59:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1760605182; x=1761209982; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:content-language:from :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=39XpzXJ9mEFd6l0WFlA738sgkk7w9+rmw36TFKBRZQ0=; b=lAUdPufm/bzFdgBHm+VygFSZsq4qWq+CKixUBG+mvYILhuaOhpP13XxWzb4MMY3i4H Iwup/0vRYFsvoh7ELWgJARTWZTr2H+aQLfdRxkqIMdHZkrRexoJ/MzJlVweCI7JyWYEa Q+o4aNqrmrJPJnYPnPqA11YpVzPnqfzVHueVUuos2r/RYLrRYPep4liuLx0Z9elFxGRn o2yr5LWEfgydvx5IXbW3ytXGucp7LD0b4BpY7ZghFvY9slfrbn4QQlRfhptcxOhynQ+y e1BUcjYiSeSM8dPK/IN1EgSkuj23RhENAKezLKEeQryobdFCvBRLT3VtN0cYBWiegef/ HOQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760605182; x=1761209982; h=content-transfer-encoding:in-reply-to:content-language:from :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=39XpzXJ9mEFd6l0WFlA738sgkk7w9+rmw36TFKBRZQ0=; b=jE4UmwHT0lsk9Vfw/uZ3Nz5wmSw6Yj475m9Oh05S3FpSjoiEIk4HLt7b+yG78IcWuL QKts0+hF5W6PmYZqrZg2lpn3j7vTTQ1DHf4XarqCkHp9CMbL5nq2gLB/xP5n7tsag2rt Iid3ixzxdpcbTqNydzlXKuToaPonnoetgw1IwfYKRNe5tBUILxozzOdMxQdQuyCtjzDD mSuLwxXPkDjCKyMbpxGBZiZWw4R+gpmys5phD4l9a/vhxDta4VCOSmNgssPlw0u+daiA r3PVkzU/cAvHltwfaKHyvCGQIqM5AuW7oKytzqxR1Q1eQ4tGMMRZLeFK9hEpc3IxTXSI 39dQ== X-Forwarded-Encrypted: i=1; AJvYcCXu89pK9d3tR8ewzD+J0vrwXftabCRyJCSumXe+wmIJWcf5njo4aWC6LR/RSjiW8FCdIGPRgVR7JsD4G0ZD@vger.kernel.org X-Gm-Message-State: AOJu0YzEXbkTE0RlGuJwvgJdkZOWFgt5TtG9vZOENy6aXecZkVuWB7t/ r2Djp8K5eVpLzZSm/L3l8afZMFUFNabvopG/pksQbN6x7nD2QBJxmRJFNCMagyaZ0ys= X-Gm-Gg: ASbGncuhM+bBCKmh/LaDZpJ2wDBbA937OXQzPfDzyxCZ0rQ/VNtTcgqFIhbFw5kMtbt 9T9EANjOt7Gk6Em2c+lsebjGWihvgyNV8WmO/z5bKyfj8Qwx2O/pnVVuXwGfQ4a8xpM/4UddyKR h2Xd3s1f2f99DTgtnRT6OYQm686RlAPoSZ0Ld6WxyWxN653kV1t31h4sLy/m7I0UYAHhwCZBktQ Uuh0q0Q7vG0+RYQ+4RVPN2gcQ80ab2138hUw2ZVK2jn5rv1aM2pUx0h4Lp+qozzsj4HGSk3ALDB jRtwFM4UtQ3DcgsPU/Wr889roxtjnXlsYBJxm0abzRUHrdmFbqdtLclc+JnI0wJXIt7PqEwTK1C geEe3IBHErUgfmxtBLoHgfro3qqNF85Ltx3NG8liwh+C7ySq/OYSn+We5FP14vF19EHPHOSW8Ra YBx54L5IvmXXF0F1VtCt4qtPBet7fwagJC5ZcjWf7LJEWtQQ== X-Google-Smtp-Source: AGHT+IFlDPa3T8k9nbZNweReXapCFa6hlD22eFQxpHRAIGN+rHEnIzDSyZpEIEHJUDE3+zn8+EsBKA== X-Received: by 2002:a05:6000:4a05:b0:426:d51c:4be8 with SMTP id ffacd0b85a97d-426d51c4d09mr14927664f8f.19.1760605182530; Thu, 16 Oct 2025 01:59:42 -0700 (PDT) Received: from [192.168.0.19] (188-141-3-146.dynamic.upc.ie. [188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426ce5d0006sm33589428f8f.34.2025.10.16.01.59.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Oct 2025 01:59:42 -0700 (PDT) Message-ID: <059a2e7b-f399-44d9-9f32-cd01e573d954@linaro.org> Date: Thu, 16 Oct 2025 09:59:40 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/6] media: qcom: camss: csiphy: Add support for v2.4.0 two-phase CSIPHY To: Hangxiang Ma , Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, aiqun.yu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, trilok.soni@oss.qualcomm.com, yijie.yang@oss.qualcomm.com, Jingyi Wang , Atiya Kailany References: <20251014-add-support-for-camss-on-kaanapali-v2-0-f5745ba2dff9@oss.qualcomm.com> <20251014-add-support-for-camss-on-kaanapali-v2-4-f5745ba2dff9@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: <20251014-add-support-for-camss-on-kaanapali-v2-4-f5745ba2dff9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 15/10/2025 03:56, Hangxiang Ma wrote: > Add more detailed resource information for CSIPHY devices in the camss > driver along with the support for v2.4.0 in the 2 phase CSIPHY driver > that is responsible for the PHY lane register configuration, module > reset and interrupt handling. > > Add 'common_status_offset' variable in 'csidphy_device_regs' structure, > which accommodates the offset between common registers and status > registers. Because this specific offset in Kaanapali registers differs > from other versions. > > Signed-off-by: Hangxiang Ma > --- > .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 147 ++++++++++++++++++++- > drivers/media/platform/qcom/camss/camss-csiphy.h | 1 + > drivers/media/platform/qcom/camss/camss.c | 107 +++++++++++++++ > 3 files changed, 249 insertions(+), 6 deletions(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index a229ba04b158..192636d02b32 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -46,7 +46,8 @@ > #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE BIT(7) > #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) > #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) > -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n)) > +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, common_status_offset, n) \ > + ((offset) + (common_status_offset) + 0x4 * (n)) > > #define CSIPHY_DEFAULT_PARAMS 0 > #define CSIPHY_LANE_ENABLE 1 > @@ -587,6 +588,123 @@ csiphy_lane_regs lane_regs_sm8550[] = { > {0x0C64, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, > }; > > +/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */ I'll again ask for a declaration of the process node this PHY sequence is fabbed on. > +static const struct > +csiphy_lane_regs lane_regs_kaanapali[] = { > + /* LN 0 */ > + {0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0094, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0000, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0008, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL}, > + {0x005C, 0x54, 0x00, CSIPHY_SKEW_CAL}, > + {0x0060, 0xFD, 0x00, CSIPHY_SKEW_CAL}, > + {0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL}, > + > + /* LN 2 */ > + {0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0490, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0494, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0400, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0408, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL}, > + {0x045C, 0x54, 0x00, CSIPHY_SKEW_CAL}, > + {0x0460, 0xFD, 0x00, CSIPHY_SKEW_CAL}, > + {0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL}, > + > + /* LN 4 */ > + {0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0890, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0894, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0800, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0808, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL}, > + {0x085C, 0x54, 0x00, CSIPHY_SKEW_CAL}, > + {0x0860, 0xFD, 0x00, CSIPHY_SKEW_CAL}, > + {0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL}, > + > + /* LN 6 */ > + {0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C00, 0x8C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL}, > + {0x0C5C, 0x54, 0x00, CSIPHY_SKEW_CAL}, > + {0x0C60, 0xFD, 0x00, CSIPHY_SKEW_CAL}, > + {0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL}, > + > + /* LN CLK */ > + {0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E94, 0x07, 0xd1, CSIPHY_DEFAULT_PARAMS}, > + {0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, > + {0x0E08, 0x19, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, > + {0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, > +}; > + > /* 4nm 2PH v 2.1.2 2p5Gbps 4 lane DPHY mode */ > static const struct > csiphy_lane_regs lane_regs_x1e80100[] = { > @@ -714,13 +832,21 @@ static void csiphy_hw_version_read(struct csiphy_device *csiphy, > CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, 6)); > > hw_version = readl_relaxed(csiphy->base + > - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 12)); > + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn( > + regs->offset, > + regs->common_status_offset, 12)); > hw_version |= readl_relaxed(csiphy->base + > - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 13)) << 8; > + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn( > + regs->offset, > + regs->common_status_offset, 13)) << 8; > hw_version |= readl_relaxed(csiphy->base + > - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 14)) << 16; > + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn( > + regs->offset, > + regs->common_status_offset, 14)) << 16; > hw_version |= readl_relaxed(csiphy->base + > - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, 15)) << 24; > + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn( > + regs->offset, > + regs->common_status_offset, 15)) << 24; This change should be separated from the addition of the PHY init sequence into its own patch so we can arbitrate that patch standalone on its merits. I have questions like "why do this" and "how does this affect other hardware" which a commit log for a change like this should spell out. > > dev_dbg(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version); > } > @@ -749,7 +875,8 @@ static irqreturn_t csiphy_isr(int irq, void *dev) > for (i = 0; i < 11; i++) { > int c = i + 22; > u8 val = readl_relaxed(csiphy->base + > - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, i)); > + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->offset, > + regs->common_status_offset, i)); > > writel_relaxed(val, csiphy->base + > CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->offset, c)); > @@ -915,6 +1042,7 @@ static bool csiphy_is_gen2(u32 version) > case CAMSS_845: > case CAMSS_8550: > case CAMSS_8775P: > + case CAMSS_KAANAPALI: > case CAMSS_X1E80100: > ret = true; > break; > @@ -989,6 +1117,7 @@ static int csiphy_init(struct csiphy_device *csiphy) > > csiphy->regs = regs; > regs->offset = 0x800; > + regs->common_status_offset = 0xb0; > > switch (csiphy->camss->res->version) { > case CAMSS_845: > @@ -1023,6 +1152,12 @@ static int csiphy_init(struct csiphy_device *csiphy) > regs->lane_regs = &lane_regs_sa8775p[0]; > regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p); > break; > + case CAMSS_KAANAPALI: > + regs->lane_regs = &lane_regs_kaanapali[0]; > + regs->lane_array_size = ARRAY_SIZE(lane_regs_kaanapali); > + regs->offset = 0x1000; > + regs->common_status_offset = 0x138; > + break; > default: > break; > } > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h > index 895f80003c44..2d5054819df7 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy.h > +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h > @@ -90,6 +90,7 @@ struct csiphy_device_regs { > const struct csiphy_lane_regs *lane_regs; > int lane_array_size; > u32 offset; > + u32 common_status_offset; > }; > > struct csiphy_device { > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index 4a5caf54c116..542122fba825 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -34,6 +34,111 @@ > > static const struct parent_dev_ops vfe_parent_dev_ops; > > +static const struct camss_subdev_resources csiphy_res_kaanapali[] = { > + /* CSIPHY0 */ > + { > + .regulators = { "vdda-phy0", "vdda-pll" }, > + .clock = { "csiphy0", "csiphy0_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy0" }, > + .interrupt = { "csiphy0" }, > + .csiphy = { > + .id = 0, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY1 */ > + { > + .regulators = { "vdda-phy1", "vdda-pll" }, > + .clock = { "csiphy1", "csiphy1_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy1" }, > + .interrupt = { "csiphy1" }, > + .csiphy = { > + .id = 1, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY2 */ > + { > + .regulators = { "vdda-phy2", "vdda-pll" }, > + .clock = { "csiphy2", "csiphy2_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy2" }, > + .interrupt = { "csiphy2" }, > + .csiphy = { > + .id = 2, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY3 */ > + { > + .regulators = { "vdda-phy3", "vdda-pll" }, > + .clock = { "csiphy3", "csiphy3_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy3" }, > + .interrupt = { "csiphy3" }, > + .csiphy = { > + .id = 3, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY4 */ > + { > + .regulators = { "vdda-phy4", "vdda-pll" }, > + .clock = { "csiphy4", "csiphy4_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy4" }, > + .interrupt = { "csiphy4" }, > + .csiphy = { > + .id = 4, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > + /* CSIPHY5 */ > + { > + .regulators = { "vdda-phy5", "vdda-pll" }, > + .clock = { "csiphy5", "csiphy5_timer", > + "cam_top_ahb", "cam_top_fast_ahb" }, > + .clock_rate = { { 400000000, 480000000 }, > + { 400000000 }, > + { 0 }, > + { 0 } }, > + .reg = { "csiphy5" }, > + .interrupt = { "csiphy5" }, > + .csiphy = { > + .id = 5, > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sdm845 > + } > + }, > +}; > + > static const struct resources_icc icc_res_kaanapali[] = { > /* Based on 4096 x 3072 30 FPS 2496 Mbps mode */ > { > @@ -4308,8 +4413,10 @@ static void camss_remove(struct platform_device *pdev) > static const struct camss_resources kaanapali_resources = { > .version = CAMSS_KAANAPALI, > .pd_name = "top", > + .csiphy_res = csiphy_res_kaanapali, > .icc_res = icc_res_kaanapali, > .icc_path_num = ARRAY_SIZE(icc_res_kaanapali), > + .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali), > }; > > static const struct camss_resources msm8916_resources = { >